platform: msm8916: add support for BLSP1 QUP4 i2c

Change to add QUP4 i2c support.

Change-Id: I935c7c93350c68893c253f606e7551fdd5ceff13
(cherry picked from commit 0251c7d)

platform/msm8916/acpuclock.c

@@ -440,12 +440,17 @@ void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
 
 	struct clk *qup_clk;
 
-	if((blsp_id != BLSP_ID_1) || (qup_id != QUP_ID_1)) {
+	if((blsp_id != BLSP_ID_1) || ((qup_id != QUP_ID_1) && (qup_id != QUP_ID_3))) {
 		dprintf(CRITICAL, "Incorrect BLSP-%d or QUP-%d configuration\n", blsp_id, qup_id);
 		ASSERT(0);
 	}
 
-	snprintf(clk_name, sizeof(clk_name), "blsp1_qup2_ahb_iface_clk");
+	if (qup_id == QUP_ID_1) {
+		snprintf(clk_name, sizeof(clk_name), "blsp1_qup2_ahb_iface_clk");
+	}
+	else if (qup_id == QUP_ID_3) {
+		snprintf(clk_name, sizeof(clk_name), "blsp1_qup4_ahb_iface_clk");
+	}
 
 	ret = clk_get_set_enable(clk_name, 0 , 1);
 
@@ -454,7 +459,12 @@ void clock_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
 		return;
 	}
 
-	snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup2_i2c_apps_clk");
+	if (qup_id == QUP_ID_1) {
+		snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup2_i2c_apps_clk");
+	}
+	else if (qup_id == QUP_ID_3) {
+		snprintf(clk_name, sizeof(clk_name), "gcc_blsp1_qup4_i2c_apps_clk");
+	}
 
 	qup_clk = clk_get(clk_name);
 

platform/msm8916/gpio.c

@@ -107,6 +107,15 @@ void gpio_config_blsp_i2c(uint8_t blsp_id, uint8_t qup_id)
 				gpio_tlmm_config(7, 3, GPIO_OUTPUT, GPIO_NO_PULL,
 					GPIO_8MA, GPIO_DISABLE);
 			break;
+			case QUP_ID_3:
+				/* configure I2C SDA gpio */
+				gpio_tlmm_config(14, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+						GPIO_8MA, GPIO_DISABLE);
+
+				/* configure I2C SCL gpio */
+				gpio_tlmm_config(15, 2, GPIO_OUTPUT, GPIO_NO_PULL,
+					GPIO_8MA, GPIO_DISABLE);
+			break;
 			default:
 				dprintf(CRITICAL, "Incorrect QUP id %d\n",qup_id);
 				ASSERT(0);

platform/msm8916/include/platform/iomap.h

@@ -111,6 +111,10 @@
 #define GCC_BLSP1_QUP2_CFG_RCGR     (CLK_CTL_BASE + 0x3018)
 #define GCC_BLSP1_QUP2_CMD_RCGR     (CLK_CTL_BASE + 0x3014)
 
+#define GCC_BLSP1_QUP4_APPS_CBCR    (CLK_CTL_BASE + 0x5020)
+#define GCC_BLSP1_QUP4_CFG_RCGR     (CLK_CTL_BASE + 0x5004)
+#define GCC_BLSP1_QUP4_CMD_RCGR     (CLK_CTL_BASE + 0x5000)
+
 /* GPLL */
 #define GPLL0_STATUS                (CLK_CTL_BASE + 0x2101C)
 #define GPLL1_STATUS                (CLK_CTL_BASE + 0x2001C)

platform/msm8916/msm8916-clock.c

@@ -591,6 +591,31 @@ static struct branch_clk gcc_blsp1_qup2_i2c_apps_clk = {
 		.ops      = &clk_ops_branch,
 	},
 };
+
+static struct rcg_clk gcc_blsp1_qup4_i2c_apps_clk_src =
+{
+	.cmd_reg      = (uint32_t *) GCC_BLSP1_QUP4_CMD_RCGR,
+	.cfg_reg      = (uint32_t *) GCC_BLSP1_QUP4_CFG_RCGR,
+	.set_rate     = clock_lib2_rcg_set_rate_hid,
+	.freq_tbl     = ftbl_gcc_blsp1_qup2_i2c_apps_clk_src,
+	.current_freq = &rcg_dummy_freq,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk_src",
+		.ops      = &clk_ops_rcg,
+	},
+};
+
+static struct branch_clk gcc_blsp1_qup4_i2c_apps_clk = {
+	.cbcr_reg = (uint32_t *) GCC_BLSP1_QUP4_APPS_CBCR,
+	.parent   = &gcc_blsp1_qup4_i2c_apps_clk_src.c,
+
+	.c = {
+		.dbg_name = "gcc_blsp1_qup4_i2c_apps_clk",
+		.ops      = &clk_ops_branch,
+	},
+};
+
 /* Clock lookup table */
 static struct clk_lookup msm_clocks_8916[] =
 {
@@ -625,6 +650,10 @@ static struct clk_lookup msm_clocks_8916[] =
 	CLK_LOOKUP("blsp1_qup2_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
 	CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk_src", gcc_blsp1_qup2_i2c_apps_clk_src.c),
 	CLK_LOOKUP("gcc_blsp1_qup2_i2c_apps_clk", gcc_blsp1_qup2_i2c_apps_clk.c),
+
+	CLK_LOOKUP("blsp1_qup4_ahb_iface_clk", gcc_blsp1_ahb_clk.c),
+	CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk_src", gcc_blsp1_qup4_i2c_apps_clk_src.c),
+	CLK_LOOKUP("gcc_blsp1_qup4_i2c_apps_clk", gcc_blsp1_qup4_i2c_apps_clk.c),
 };
 
 void msm8939_clock_override()