32-bit RISC-V CPU in ~800 lines of C89

VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes

Mirror of: https://git.beagleboard.org/beaglev-ahead/xuantie-ubuntu

An optimized neural network operator library for chips base on Xuantie CPU.

A try to make software slave I2C driver

In application debugger for ARM Cortex microcontrollers.

NEORV32 and a generic FAT file system called FatFs.

Xilinx Embedded Software (embeddedsw) Development

Open source FPGA-based NIC and platform for in-network compute

Fork of OpenOCD that has RISC-V support

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

🐛 JTAG debug transport module (DTM) - compatible to the RISC-V debug specification.

A XModem Bootloader for the NEORV32 CPU on the DE0-Nano board.

A tiny C header-only risc-v emulator.

The repository provides code for running inference with the SegmentAnything Model (SAM), links for downloading the trained model checkpoints, and example notebooks that show how to use the model.

M1s_BL808_example

Plugin to generate BOM + CPL files for JLCPCB, assigning LCSC part numbers directly from the plugin, query the JLCPCB parts database, lookup datasheets and much more.

Tools for reading and writing identification EEPROMs on NVIDIA Jetson platforms.

MIPI CSI-2 RX

Open source ISS and logic RISC-V 32 bit project

I2C Slave Interface (Vhdl)

Lattice Crosslink FPGA is programmed to simulate an IMX219 image stream to a Jetson Nano

🖥️ A small, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

Antmicro's open hardware 3G SDI into MIPI CSI-2 converter

Development board for Lattice Crosslink-NX 72QFN