3-stage RV32IMACZb* processor with debug

Monorepo for a random selection of parts designed in CadQuery

Reusable Verilog 2005 components for FPGA designs

Bitbanged DVI on the RP2040 Microcontroller

Loose collection of scripts for FPGA work

Turn WaveDrom timing diagrams into ASCII art

Portable games console, designed from scratch: CPU, graphics, PCB, and the kitchen sink

5-stage RISC-V CPU, originally developed for RISCBoy

Dual-RP2040 development board with built-in debug

Example Hazard3 + OpenDAP RISC-V SWD SoC integration

Minimal RV32I processor with register file in RAM

Yet Another Debug Transport

Dual-core RISC-V SoC with JTAG, atomics, SDRAM