无外部依赖，快速为相片添加exif边框 | exif frame in an instant without external dependence

🆙 Upscayl - #1 Free and Open Source AI Image Upscaler for Linux, MacOS and Windows.

OpenTitan: Open source silicon root of trust

An FPGA-based Ultra-High Throughput JPEG-LS encoder, which provides lossless image compression. 一个超高性能的FPGA JPEG-LS编码器，用来进行无损图像压缩。

AMBA bus lecture material

VeeR EH1 core

体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器

UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

An FPGA-based Field Oriented Control (FOC) for driving BLDC/PMSM motor. 基于FPGA的FOC控制器，用于驱动BLDC/PMSM电机。

A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz

这是一个用于显示当前网速、CPU及内存利用率的桌面悬浮窗软件，并支持任务栏显示，支持更换皮肤。

beamer template collection

YOLOv5 🚀 in PyTorch > ONNX > CoreML > TFLite

FPGA project

EDID repository for LCD monitors

Various HDL (Verilog) IP Cores

TinyMaix is a tiny inference library for microcontrollers (TinyML).

RISC-V CPU Core (RV32IM)

synthesiseable ieee 754 floating point library in verilog

Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.

Verilog library for ASIC and FPGA designers

a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Nuclei Board Labs

ThesisUESTC-电子科技大学毕业论文模板

LicheeTang FPGA Examples