Pinned Loading

1. Xilinx-NEXYS4_DDR-Drives-OV5640 Xilinx-NEXYS4_DDR-Drives-OV5640 Public

   The aiming of this project is to realize the image capture using OV5640 camera and FPGA which transmits the image signal using VGA (Video Graphic Array) standard on an LCD screen.

   VHDL 18 6

2. pulpino_fpga_chip_test pulpino_fpga_chip_test Public

   test the pulpino chip with zedboard

   SystemVerilog

3. VerilogA-Voltage_Controll_Oscillator VerilogA-Voltage_Controll_Oscillator Public

   Verilog-A Modeling: Voltage Controlled Oscillator

   2 1

4. ZYNQ-Write_to_BRAM ZYNQ-Write_to_BRAM Public

   VHDL