Add axi_to_mem_banked and test

YL29399 · Aug 29, 2022 · fec8d2e · fec8d2e
1 parent 620a493
commit fec8d2e
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Showing 12 changed files with 987 additions and 4 deletions.
diff --git a/.ci/Memora.yml b/.ci/Memora.yml
@@ -258,6 +258,21 @@ artifacts:
     outputs:
       - build/axi_to_axi_lite-%.tested
 
+  axi_to_mem_banked-%:
+    inputs:
+      - Bender.yml
+      - include
+      - scripts/run_vsim.sh
+      - src/axi_pkg.sv
+      - src/axi_intf.sv
+      - src/axi_test.sv
+      - src/axi_demux.sv
+      - src/axi_to_mem.sv
+      - src/axi_to_mem_banked.sv
+      - test/tb_axi_to_mem_banked.sv
+    outputs:
+      - build/axi_to_mem_banked-%.tested
+
   axi_xbar-%:
     inputs:
       - Bender.yml

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -28,7 +28,7 @@ vsim:
       fi
   parallel:
     matrix:
-      - VSIM_VER: ['10.7b', '10.7e', '2020.1', '2021.1']
+      - VSIM_VER: ['10.7b', '10.7e', '2021.3']
 
 synopsys_dc:
   stage: build
@@ -61,7 +61,7 @@ synopsys_dc:
       fi
   parallel:
     matrix:
-      - VSIM_VER: ['10.7b', '10.7e', '2020.1', '2021.1']
+      - VSIM_VER: ['10.7b', '10.7e', '2021.3']
 
 axi_addr_test:
   <<: *run_vsim
@@ -148,6 +148,11 @@ axi_to_axi_lite:
   variables:
     TEST_MODULE: axi_to_axi_lite
 
+axi_to_mem_banked:
+  <<: *run_vsim
+  variables:
+    TEST_MODULE: axi_to_mem_banked
+
 axi_xbar:
   <<: *run_vsim
   variables:

diff --git a/Bender.yml b/Bender.yml
@@ -10,6 +10,7 @@ package:
 dependencies:
   common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.26.0 }
   common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
+  tech_cells_generic:  { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.2 }
 
 export_include_dirs:
   - include
@@ -55,6 +56,7 @@ sources:
   - src/axi_id_serialize.sv
   - src/axi_multicut.sv
   - src/axi_to_axi_lite.sv
+  - src/axi_to_mem_banked.sv
   # Level 4
   - src/axi_iw_converter.sv
   - src/axi_lite_xbar.sv
@@ -92,4 +94,5 @@ sources:
       - test/tb_axi_serializer.sv
       - test/tb_axi_sim_mem.sv
       - test/tb_axi_to_axi_lite.sv
+      - test/tb_axi_to_mem_banked.sv
       - test/tb_axi_xbar.sv
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -13,6 +13,9 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
   scoreboard class.
 - `axi_throttle`: Add a module that limits the maximum number of outstanding transfers sent to the
   downstream logic.
+- `axi_to_mem_banked`:  AXI4+ATOP slave to control on chip memory, with banking support, higher
+                        throughput than `axi_to_mem`.
+- `Bender`: Add dependency `tech_cells_generic` `v0.2.2` for generic SRAM macro for simulation.
 
 ### Changed
 

diff --git a/README.md b/README.md
@@ -54,7 +54,7 @@ In addition to the documents linked in the following table, we are setting up [d
 | [`axi_throttle`](src/axi_throttle.sv)                | Limits the maximum number of outstanding transfers sent to the downstream logic.                  |                                |
 | [`axi_test`](src/axi_test.sv)                        | A set of testbench utilities for AXI interfaces.                                                  |                                |
 | [`axi_to_axi_lite`](src/axi_to_axi_lite.sv)          | AXI4 to AXI4-Lite protocol converter.                                                             |                                |
-| [`axi_to_mem`](src/axi_to_mem.sv)                    | AXI4 to memory protocol (req, gnt, rvalid) converter.                                             |                                |
+| [`axi_to_mem`](src/axi_to_mem.sv)                    | AXI4 to memory protocol (req, gnt, rvalid) converter. Additional banked variant.                  |                                |
 | [`axi_xbar`](src/axi_xbar.sv)                        | Fully-connected AXI4+ATOP crossbar with an arbitrary number of slave and master ports.            | [Doc](doc/axi_xbar.md)         |
 
 ### Simulation-Only Modules

diff --git a/axi.core b/axi.core
@@ -47,6 +47,7 @@ filesets:
       - src/axi_id_serialize.sv
       - src/axi_multicut.sv
       - src/axi_to_axi_lite.sv
+      - src/axi_to_mem_banked.sv
       # Level 4
       - src/axi_iw_converter.sv
       - src/axi_lite_xbar.sv

diff --git a/scripts/compile_vsim.sh b/scripts/compile_vsim.sh
@@ -18,7 +18,7 @@ set -e
 
 [ ! -z "$VSIM" ] || VSIM=vsim
 
-bender script vsim -t test \
+bender script vsim -t test -t rtl \
     --vlog-arg="-svinputport=compat" \
     --vlog-arg="-override_timescale 1ns/1ps" \
     --vlog-arg="-suppress 2583" \

diff --git a/scripts/run_vsim.sh b/scripts/run_vsim.sh
@@ -174,6 +174,27 @@ exec_test() {
                 done
             done
             ;;
+        axi_to_mem_banked)
+            for MEM_LAT in 1 2; do
+                for BANK_FACTOR in 1 2; do
+                    for NUM_BANKS in 1 2 ; do
+                        for AXI_DATA_WIDTH in 64 256 ; do
+                            ACT_BANKS=$((2*$BANK_FACTOR*$NUM_BANKS))
+                            MEM_DATA_WIDTH=$(($AXI_DATA_WIDTH/$NUM_BANKS))
+                            call_vsim tb_axi_to_mem_banked \
+                                -voptargs="+acc +cover=bcesfx" \
+                                -gTbAxiDataWidth=$AXI_DATA_WIDTH \
+                                -gTbNumWords=2048 \
+                                -gTbNumBanks=$ACT_BANKS \
+                                -gTbMemDataWidth=$MEM_DATA_WIDTH \
+                                -gTbMemLatency=$MEM_LAT \
+                                -gTbNumWrites=2000 \
+                                -gTbNumReads=2000
+                        done
+                    done
+                done
+            done
+            ;;
         *)
             call_vsim tb_$1 -t 1ns -coverage -voptargs="+acc +cover=bcesfx"
             ;;