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Add C++ VexRiscv model to cross check the hardware simulation
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@Dolu1990
Dolu1990 committed Aug 22, 2018
1 parent 38af5db commit 7ed6835
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Showing 15 changed files with 151 additions and 96 deletions.
4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenFull.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object GenFull extends App{
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false
),
new IBusCachedPlugin(
Expand Down Expand Up @@ -63,7 +63,7 @@ object GenFull extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
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4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenFullNoMmu.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object GenFullNoMmu extends App{
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false
),
new IBusCachedPlugin(
Expand Down Expand Up @@ -55,7 +55,7 @@ object GenFullNoMmu extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
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4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object GenFullNoMmuMaxPerf extends App{
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false
),
new IBusCachedPlugin(
Expand Down Expand Up @@ -56,7 +56,7 @@ object GenFullNoMmuMaxPerf extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
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4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object GenFullNoMmuNoCache extends App{
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false,
prediction = STATIC,
catchAccessFault = false,
Expand All @@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
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2 changes: 1 addition & 1 deletion src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ object GenNoCacheNoMmuMaxPerf extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
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4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ object GenSmallAndProductive extends App{
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false,
prediction = NONE,
catchAccessFault = false,
Expand All @@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenSmallAndPerformantICache.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ object GenSmallAndProductiveICache extends App{
config = VexRiscvConfig(
plugins = List(
new PcManagerSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false
),
new IBusCachedPlugin(
Expand Down Expand Up @@ -42,7 +42,7 @@ object GenSmallAndProductiveICache extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenSmallest.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ object GenSmallest extends App{
config = VexRiscvConfig(
plugins = List(
new IBusSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false,
prediction = NONE,
catchAccessFault = false,
Expand All @@ -28,7 +28,7 @@ object GenSmallest extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
Expand Down
4 changes: 2 additions & 2 deletions src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ object GenSmallestNoCsr extends App{
// ),

new IBusSimplePlugin(
resetVector = 0x00000000l,
resetVector = 0x80000000l,
relaxedPcCalculation = false,
prediction = NONE,
catchAccessFault = false,
Expand All @@ -33,7 +33,7 @@ object GenSmallestNoCsr extends App{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false,
zeroBoot = true,
writeRfInMemoryStage = false
),
new IntAluPlugin,
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,7 @@ object VexRiscvAvalonForSim{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
Expand Down
2 changes: 1 addition & 1 deletion src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -80,7 +80,7 @@ object VexRiscvAvalonWithIntegratedJtag{
),
new RegFilePlugin(
regFileReadyKind = plugin.SYNC,
zeroBoot = false
zeroBoot = true
),
new IntAluPlugin,
new SrcPlugin(
Expand Down
52 changes: 16 additions & 36 deletions src/main/scala/vexriscv/plugin/CsrPlugin.scala
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Original file line number Diff line number Diff line change
Expand Up @@ -376,17 +376,6 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio

val mepcCaptureStage = if(exceptionPortsInfos.nonEmpty) writeBack else decode

//Used to make the pipeline empty softly (for interrupts)
val pipelineLiberator = new Area{
val enable = False.noBackendCombMerge //Verilator Perf
when(enable && decode.arbitration.isValid){
decode.arbitration.haltByOther := True
}
//TODO !!! can lose instruction that had exception !!!!
val done = !List(execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage)
}



//Aggregate all exception port and remove required instructions
val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{
Expand Down Expand Up @@ -470,32 +459,24 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
}
}
}
// val deteriministicLogic = if(deterministicInteruptionEntry) new Area{
// val counter = Reg(UInt(4 bits)) init(0)
// val limit = Reg(UInt(4 bits)) init(5)
// when(interruptRequest.rise()){
// limit := CountOne(stages.tail.map(_.arbitration.isValid)).resized
// }
// when(!interruptRequest || !mstatus.MIE){
// counter := 0
// } otherwise {
// when(counter < limit){
// when(writeBack.arbitration.isFiring){
// counter := counter + 1
// }
// }
// val counterPlusPending = counter + CountOne(stages.tail.map(_.arbitration.isValid)) + 1
// when(counterPlusPending < limit){
// inhibateInterrupts()
// }
// }
// }


//Used to make the pipeline empty softly (for interrupts)
val pipelineLiberator = new Area{
when(interrupt && decode.arbitration.isValid){
decode.arbitration.haltByOther := True
}

val done = !List(execute, memory, writeBack).map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage)
if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR)
}

//Interrupt/Exception entry logic
pipelineLiberator.enable setWhen(interrupt)
val interruptCode = ((mip.MEIP && mie.MEIE) ? U(11) | ((mip.MSIP && mie.MSIE) ? U(3) | U(7))).addTag(Verilator.public)
val interruptJump = False.addTag(Verilator.public)
when(exception || (interrupt && pipelineLiberator.done)){ //TODO remove interrupt &&
val interruptJump = Bool.addTag(Verilator.public)
interruptJump := interrupt && pipelineLiberator.done

when(exception || interruptJump){
jumpInterface.valid := True
jumpInterface.payload := mtvec
memory.arbitration.flushAll := True
Expand All @@ -504,9 +485,8 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
mstatus.MPIE := mstatus.MIE
mstatus.MPP := privilege
mepc := mepcCaptureStage.input(PC)
mcause.interrupt := interrupt
mcause.interrupt := interruptJump
mcause.exceptionCode := interruptCode
interruptJump := interrupt;
}

when(RegNext(exception)){
Expand Down
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