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Commits on Sep 10, 2020

• libtrellis: Add missing map include

  Show description for 9447f22
  gatecat

  committed
  9447f22

Commits on Sep 9, 2020

• devices.json: Fix accidentally dropped device

  Show description for 997ca24
  gatecat

  committed
  997ca24

• tools: Fix HTML index output

  Show description for 4357600
  gatecat

  committed
  4357600

• Update database to master

  Show description for af32b34
  gatecat

  committed
  af32b34

• Merge pull request #148 from cr1901/facade

  Show description for d701ba9
  gatecat

  authored
  d701ba9

• Bring in database PCI CLAMP changes.

  cr1901

  committed
  cefbc0b

• Fix PCI CLAMP and DIFFDRIVE fuzzers to produce correct data (DIFFDRIVE out of scope until PIC_T_DUMMY_VIQ is fuzzed).

  cr1901

  committed
  3890ed8

• Bring in database changes.

  cr1901

  committed
  9f9e607

• Use hyphen instead of underscore for 'missing-dccs' field in globals.json.

  cr1901

  committed
  a9e765a

Commits on Sep 7, 2020

• Bring commented in RoutingGraph up to date and remove commented-out code.

  cr1901

  committed
  4af7ea0

• Merge branch 'master' of https://github.com/YosysHQ/prjtrellis into facade

  cr1901

  committed
  db94108

• Remove EFB.v- ask user to regenerate if necessary.

  cr1901

  committed
  52c31c1

• Generate globals.json for each MachXO2 device on-the-fly- remove metadata directory.

  cr1901

  committed
  a4f30ac

• Fix overeager find and replace in Chip.cpp.

  cr1901

  committed
  23e1cdd

• Document that 021-glb-entry has only been done for CENTER_EBR_CIB tiles

  Show description for 8b7845f
  cr1901

  committed
  8b7845f

• Remove ccu2_mux and center_mux experiment output diffs- can be regenerated if necessary.

  cr1901

  committed
  3f639e5

• Restore devices.json to original state.

  cr1901

  committed
  ae0a7d4

Commits on Aug 26, 2020

• fuzzers: Add missing JPADDI[AC]->JPADDI arc

  Show description for 389c251
  gatecat

  committed
  389c251

Commits on Aug 22, 2020

• Allow Chip.global_data as backwards-compatible alias for for Chip.global_data_ecp5.

  cr1901

  committed
  7428bfc

Commits on Aug 21, 2020

• Switch submodule back to upstream repo.

  cr1901

  committed
  3babbaf

• Clean up find_machxo2_global_position a bit more.

  cr1901

  committed
  a81ceb1

• Refactor regex handler in find_machxo2_global_position.

  cr1901

  committed
  4ed6c3f

Commits on Aug 17, 2020

• Merge branch 'master' of https://github.com/YosysHQ/prjtrellis into facade

  cr1901

  committed
  c684650

Commits on Aug 16, 2020

• Connect U_/D_ globals to BRANCHes, completing global routing connections.

  cr1901

  committed
  e761744

• Bring in database changes.

  cr1901

  committed
  f54dd28

• Avoid copying nonexistent DCC mux bits in row 11.

  cr1901

  committed
  b8523e6

• Forgot to route DCC outputs to the rest of global network.

  cr1901

  committed
  e162697

• Special-case routing sink whose config bits span across multiple tiles when building the routing graph.

  cr1901

  committed
  ef67e9f

• Covert find_machxo2_global_position to use regexes- find isn't precise enough.

  cr1901

  committed
  7bd7301

Commits on Aug 15, 2020

• Add missing BELs, fix DCCA/DCMA naming, and start assigning nominal positions to globals connected to missing BELs (checkpoint commit).

  cr1901

  committed
  0401e80

Commits on Aug 14, 2020

• Inject MachXO2 globals info into RoutingGraph. Create stub BRANCH handling, and handle "DCC" globals connecting L/R to U/D.

  cr1901

  committed
  811a2da

• L/R and U/D conns should not be copied to CIB_PIC_{B0, B_DUMMY} tiles.

  cr1901

  committed
  c4c9f0d

• Fix bad tile name matching again- was accidentally reverted in 874d12b.

  cr1901

  committed
  e8a33c9

Commits on Aug 12, 2020

• Add missing Python class which maps Location to LocationData (for OptimizedChipdb).

  Show description for 98246ba
  cr1901

  committed
  98246ba

Commits on Aug 7, 2020

• Merge remote-tracking branch 'origin' into facade

  cr1901

  committed
  e28ac1f

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