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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Verilog AXI components for FPGA implementation
Utility for embedding code snippets into markdown documents
DISN: Deep Implicit Surface Network for High-quality Single-view 3D Reconstruction
M.S. 101, Graduate Institute of Electronics Engineering, National Taiwan University
National Taiwan University Master's Thesis Template (Latex + Word)
We estimate dense, flicker-free, geometrically consistent depth from monocular video, for example hand-held cell phone video.
The official code repository for examples in the O'Reilly book 'Generative Deep Learning'
Taking a Deeper Look at the Inverse Compositional Algorithm (CVPR 2019, Oral)
Particle filtering and sequential parameter inference in Python
opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
GoogleTest - Google Testing and Mocking Framework
CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
Kalman Filter book using Jupyter Notebook. Focuses on building intuition and experience, not formal proofs. Includes Kalman filters,extended Kalman filters, unscented Kalman filters, particle filte…
Tutorial on "Modern Optimization Methods in Python"
Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies
Image augmentation for machine learning experiments.