Turns Data and AI algorithms into production-ready web applications in no time.

TEE hardware - based on the chipyard repository - hardware to accelerate TEE

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Rocket Chip Generator

NVDLA is an Open source DL/ML accelerator, which is very suitable for individuals or college students. This is the NOTES when I learn and try. Hope THIS PAGE may Helps you a bit. Contact Me:junning…

Small footprint and configurable DRAM core

分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。

Superscalar OoO RISCV processor written in Chisel

Linux kernel source tree

An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

The code for "Image-Adaptive YOLO for Object Detection in Adverse Weather Conditions (AAAI 2022)"

深澜校园网登录程序 Go 语言版，适用于Windows、Linux、路由器等。提供对 Docker、Go Module、OpenWrt 的支持

Pytorch Implementations of large number classical backbone CNNs, data enhancement, torch loss, attention, visualization and some common algorithms.

Rocket Chip Generator

SonicBOOM: The Berkeley Out-of-Order Machine

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

IC design and development should be faster，simpler and more reliable

PicoRV32 - A Size-Optimized RISC-V CPU

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

汇聚【Python应用】【Python实训】【Python技术分享】等等