OpenRISC processor IP core based on Tomasulo algorithm

mor1kx - an OpenRISC 1000 processor IP core

OpenRISC 1200 implementation

Mt-KaHyPar (Multi-Threaded Karlsruhe Hypergraph Partitioner) is a shared-memory multilevel graph and hypergraph partitioner equipped with parallel implementations of techniques used in the best seq…

Source code for AAAI 2022 paper: Unified Named Entity Recognition as Word-Word Relation Classification

Named-Entity-Recognition-with-Bidirectional-LSTM-CNNs

Tensorflow implementation of contextualized word representations from bi-directional language models

This is an official implementation for "DeepGate: Learning Neural Representations of Logic Gates".

Yosys Open SYnthesis Suite

Timing prediction dataset download and instructions.

ONNX Runtime: cross-platform, high performance ML inferencing and training accelerator

全国各省市停贷通知汇总

This repository contains the CUDA implementation of the paper "Work-efficient Parallel Non-Maximum Suppression Kernels".

Parallel CUDA implementation of NON maximum Suppression

Image classification with NVIDIA TensorRT from TensorFlow models.

THIS REPOSITORY HAS MOVED TO github.com/nvidia/cub, WHICH IS AUTOMATICALLY MIRRORED HERE.

A detailed data mining and ML experiment carried out for a sports activity dataset using python + W.E.K.A

tensorboard for pytorch (and chainer, mxnet, numpy, ...)

PACoGen: Posit Arithmetic Core Generator

Library of approximate arithmetic circuits

A functional ALU circuit implemented in Verilog. Includes dedicated adder, subtractor, multiplier, divider, comparator, and shifter blocks.

32-bit Divider circuit implemented using Verilog

Prefix adder generators for Verilog

This script generates and analyzes prefix tree adders.

FIT BUT bachelor's degree project

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.