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A versatile toolkit for programmable on-chip network generation and simulation

Scala 9 Updated Oct 24, 2022

SystemVerilog linter

Rust 318 33 Updated Sep 13, 2024

An integrated CGRA design framework

Scala 83 13 Updated Nov 11, 2024

A hardware compiler based on LLHD and CIRCT

Rust 250 31 Updated Sep 30, 2023