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Update to Capstone master 5742a15
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reverser committed Apr 23, 2015
1 parent 0e8ff9e commit 3431351
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Showing 39 changed files with 46,503 additions and 45,882 deletions.
6 changes: 3 additions & 3 deletions Info.plist
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Expand Up @@ -3,9 +3,9 @@
<plist version="1.0">
<dict>
<key>CFBuildDate</key>
<string>Thu Nov 20 11:30:21 WET 2014</string>
<string>Thu Apr 23 12:18:08 WEST 2015</string>
<key>CFBuildNumber</key>
<string>9113</string>
<string>9121</string>
<key>CFBundleDevelopmentRegion</key>
<string>English</string>
<key>CFBundleDocumentTypes</key>
Expand Down Expand Up @@ -44,7 +44,7 @@
<key>CFBundleSignature</key>
<string>????</string>
<key>CFBundleVersion</key>
<string>9113</string>
<string>9121</string>
<key>LSApplicationCategoryType</key>
<string>public.app-category.developer-tools</string>
<key>LSMinimumSystemVersion</key>
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5 changes: 5 additions & 0 deletions capstone/MCInst.c
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@@ -1,8 +1,12 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <[email protected]>, 2013-2014 */

#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdio.h>
#include <stdlib.h>
#endif
#include <string.h>

#include "MCInst.h"
Expand All @@ -16,6 +20,7 @@ void MCInst_Init(MCInst *inst)
inst->size = 0;
inst->has_imm = false;
inst->op1_size = 0;
inst->writeback = false;
}

void MCInst_clear(MCInst *inst)
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1 change: 1 addition & 0 deletions capstone/MCInst.h
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Expand Up @@ -106,6 +106,7 @@ struct MCInst {
// This is copied from cs_x86 struct
uint8_t x86_prefix[4];
uint8_t imm_size; // immediate size for X86_OP_IMM operand
bool writeback; // writeback for ARM
};

void MCInst_Init(MCInst *inst);
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12 changes: 6 additions & 6 deletions capstone/MCInstrDesc.h
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Expand Up @@ -120,20 +120,20 @@ enum {
/// this struct directly to describe itself.
typedef struct MCInstrDesc {
unsigned short Opcode; // The opcode number
unsigned short NumOperands; // Num of args (may be more if variable_ops)
unsigned short NumDefs; // Num of args that are definitions
unsigned char NumOperands; // Num of args (may be more if variable_ops)
unsigned char NumDefs; // Num of args that are definitions
unsigned short SchedClass; // enum identifying instr sched class
unsigned short Size; // Number of bytes in encoding.
unsigned char Size; // Number of bytes in encoding.
unsigned Flags; // Flags identifying machine instr class
uint64_t TSFlags; // Target Specific Flag values
uint16_t *ImplicitUses; // Registers implicitly read by this instr
uint16_t *ImplicitDefs; // Registers implicitly defined by this instr
char ImplicitUses; // Registers implicitly read by this instr
char ImplicitDefs; // Registers implicitly defined by this instr
MCOperandInfo *OpInfo; // 'NumOperands' entries about operands
uint64_t DeprecatedFeatureMask;// Feature bits that this is deprecated on, if any
// A complex method to determine is a certain is deprecated or not, and return
// the reason for deprecation.
//bool (*ComplexDeprecationInfo)(MCInst &, MCSubtargetInfo &, std::string &);
unsigned ComplexDeprecationInfo; // dummy field, just to satisfy initializer
unsigned char ComplexDeprecationInfo; // dummy field, just to satisfy initializer
} MCInstrDesc;

bool MCOperandInfo_isPredicate(MCOperandInfo *m);
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14 changes: 13 additions & 1 deletion capstone/SStream.c
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Expand Up @@ -3,12 +3,16 @@

#include <stdint.h>
#include <stdarg.h>
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <libkern/libkern.h>
#else
#include <stdio.h>
#endif
#include <string.h>

#include "SStream.h"
#include "cs_priv.h"
#include "inttypes.h"
#include "myinttypes.h"
#include "utils.h"

#ifdef _MSC_VER
Expand Down Expand Up @@ -61,6 +65,14 @@ void printInt64Bang(SStream *O, int64_t val)
}
}

void printUInt64Bang(SStream *O, uint64_t val)
{
if (val > HEX_THRESHOLD)
SStream_concat(O, "#0x%"PRIx64, val);
else
SStream_concat(O, "#%"PRIu64, val);
}

// print number
void printInt64(SStream *O, int64_t val)
{
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2 changes: 2 additions & 0 deletions capstone/SStream.h
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Expand Up @@ -17,6 +17,8 @@ void SStream_concat0(SStream *ss, char *s);

void printInt64Bang(SStream *O, int64_t val);

void printUInt64Bang(SStream *O, uint64_t val);

void printInt64(SStream *O, int64_t val);

void printInt32Bang(SStream *O, int32_t val);
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3 changes: 2 additions & 1 deletion capstone/arch/AArch64/AArch64Disassembler.c
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Expand Up @@ -224,6 +224,7 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,
{
uint32_t insn;
DecodeStatus result;
size_t i;

if (code_len < 4) {
// not enough data
Expand All @@ -233,7 +234,7 @@ static DecodeStatus _getInstruction(cs_struct *ud, MCInst *MI,

if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
for (size_t i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm64.operands); i++)
MI->flat_insn->detail->arm64.operands[i].vector_index = -1;
}

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20 changes: 13 additions & 7 deletions capstone/arch/AArch64/AArch64InstPrinter.c
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Expand Up @@ -16,7 +16,7 @@

#ifdef CAPSTONE_HAS_ARM64

#include "../../inttypes.h"
#include "../../myinttypes.h"
#include <stdio.h>
#include <stdlib.h>

Expand Down Expand Up @@ -333,7 +333,8 @@ static bool printSysAlias(MCInst *MI, SStream *O)
unsigned CnVal = (unsigned)MCOperand_getImm(Cn);
unsigned CmVal = (unsigned)MCOperand_getImm(Cm);
unsigned Op2Val = (unsigned)MCOperand_getImm(Op2);
unsigned insn_id, op_ic = 0, op_dc = 0, op_at = 0, op_tlbi = 0;
unsigned insn_id = ARM64_INS_INVALID;
unsigned op_ic = 0, op_dc = 0, op_at = 0, op_tlbi = 0;

if (CnVal == 7) {
switch (CmVal) {
Expand Down Expand Up @@ -605,12 +606,16 @@ static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
}
}
} else if (MCOperand_isImm(Op)) {
int imm = (int)MCOperand_getImm(Op);
printInt32Bang(O, imm);
int64_t imm = MCOperand_getImm(Op);

if (MI->Opcode == AArch64_ADR) {
imm += MI->address;
printUInt64Bang(O, imm);
} else
printUInt64Bang(O, imm);
if (MI->csh->detail) {
if (MI->csh->doing_mem) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = imm;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].mem.disp = (int32_t)imm;
} else {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
Expand Down Expand Up @@ -1238,10 +1243,11 @@ static void printAlignedLabel(MCInst *MI, unsigned OpNum, SStream *O)
// If the label has already been resolved to an immediate offset (say, when
// we're running the disassembler), just print the immediate.
if (MCOperand_isImm(Op)) {
printInt64Bang(O, MCOperand_getImm(Op) << 2);
uint64_t imm = (MCOperand_getImm(Op) << 2) + MI->address;
printUInt64Bang(O, imm);
if (MI->csh->detail) {
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].type = ARM64_OP_IMM;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = (int)MCOperand_getImm(Op) << 2;
MI->flat_insn->detail->arm64.operands[MI->flat_insn->detail->arm64.op_count].imm = imm;
MI->flat_insn->detail->arm64.op_count++;
}
return;
Expand Down
4 changes: 2 additions & 2 deletions capstone/arch/AArch64/AArch64Mapping.c
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Expand Up @@ -832,13 +832,13 @@ static insn_map insns[] = {
{
AArch64_BL, ARM64_INS_BL,
#ifndef CAPSTONE_DIET
{ ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0
{ 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0
#endif
},
{
AArch64_BLR, ARM64_INS_BLR,
#ifndef CAPSTONE_DIET
{ ARM64_REG_SP, 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0
{ 0 }, { ARM64_REG_LR, 0 }, { 0 }, 0, 0
#endif
},
{
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10 changes: 4 additions & 6 deletions capstone/arch/ARM/ARMDisassembler.c
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Expand Up @@ -15,7 +15,7 @@
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include "../../inttypes.h"
#include "../../myinttypes.h"

#include "ARMAddressingModes.h"
#include "ARMBaseInfo.h"
Expand Down Expand Up @@ -450,8 +450,6 @@ static DecodeStatus _ARM_getInstruction(cs_struct *ud, MCInst *MI, const uint8_t
// not enough data
return MCDisassembler_Fail;

ud->ITBlock.size = 0;

if (MI->flat_insn->detail) {
memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
Expand Down Expand Up @@ -687,17 +685,16 @@ static DecodeStatus _Thumb_getInstruction(cs_struct *ud, MCInst *MI, const uint8
bool InITBlock;
unsigned Firstcond, Mask;
uint32_t NEONLdStInsn, insn32, NEONDataInsn, NEONCryptoInsn, NEONv8Insn;
size_t i;

// We want to read exactly 2 bytes of data.
if (code_len < 2)
// not enough data
return MCDisassembler_Fail;

ud->ITBlock.size = 0;

if (MI->flat_insn->detail) {
memset(&MI->flat_insn->detail->arm, 0, sizeof(cs_arm));
for (size_t i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
for (i = 0; i < ARR_SIZE(MI->flat_insn->detail->arm.operands); i++)
MI->flat_insn->detail->arm.operands[i].vector_index = -1;
}

Expand Down Expand Up @@ -1772,6 +1769,7 @@ static DecodeStatus DecodeAddrMode3Instruction(MCInst *Inst, unsigned Insn,
}

if (writeback) { // Writeback
Inst->writeback = true;
if (P)
U |= ARMII_IndexModePre << 9;
else
Expand Down
30 changes: 15 additions & 15 deletions capstone/arch/ARM/ARMGenInstrInfo.inc
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Expand Up @@ -2814,21 +2814,21 @@ enum {

#define nullptr 0

static uint16_t ImplicitList1[] = { ARM_CPSR, 0 };
static uint16_t ImplicitList2[] = { ARM_SP, 0 };
static uint16_t ImplicitList3[] = { ARM_LR, 0 };
static uint16_t ImplicitList4[] = { ARM_FPSCR_NZCV, 0 };
static uint16_t ImplicitList5[] = { ARM_R7, ARM_LR, ARM_SP, 0 };
static uint16_t ImplicitList6[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static uint16_t ImplicitList7[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static uint16_t ImplicitList8[] = { ARM_R0, ARM_R12, ARM_LR, ARM_CPSR, 0 };
static uint16_t ImplicitList9[] = { ARM_FPSCR, 0 };
static uint16_t ImplicitList10[] = { ARM_R4, 0 };
static uint16_t ImplicitList11[] = { ARM_R4, ARM_SP, 0 };
static uint16_t ImplicitList12[] = { ARM_ITSTATE, 0 };
static uint16_t ImplicitList13[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_CPSR, ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15, 0 };
static uint16_t ImplicitList14[] = { ARM_PC, 0 };
static uint16_t ImplicitList15[] = { ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R12, ARM_CPSR, 0 };
#define ImplicitList1 0
#define ImplicitList2 0
#define ImplicitList3 0
#define ImplicitList4 0
#define ImplicitList5 0
#define ImplicitList6 0
#define ImplicitList7 0
#define ImplicitList8 0
#define ImplicitList9 0
#define ImplicitList10 0
#define ImplicitList11 0
#define ImplicitList12 0
#define ImplicitList13 0
#define ImplicitList14 0
#define ImplicitList15 0

static MCOperandInfo OperandInfo2[] = { { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
static MCOperandInfo OperandInfo3[] = { { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_UNKNOWN, 0 }, { -1, 0, MCOI_OPERAND_IMMEDIATE, 0 }, };
Expand Down
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