Reduce width of refresh counter.

abhayjb · Jun 20, 2015 · 74cabef · 74cabef
1 parent 0fb8c2b
commit 74cabef
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Showing 3 changed files with 6 additions and 3 deletions.
diff --git a/ftdi_async_bridge/sw/makefile b/ftdi_async_bridge/sw/makefile
@@ -9,6 +9,7 @@ all:
 	make -f makefile.mk TARGET=verify
 	make -f makefile.mk TARGET=gpio_read
 	make -f makefile.mk TARGET=gpio_write
+	make -f makefile.mk TARGET=sdram_test
 
 clean:
 	make -f makefile.mk TARGET=load clean
@@ -18,3 +19,5 @@ clean:
 	make -f makefile.mk TARGET=verify clean
 	make -f makefile.mk TARGET=gpio_read clean
 	make -f makefile.mk TARGET=gpio_write clean
+	make -f makefile.mk TARGET=sdram_test clean
+
diff --git a/sdram/README.md b/sdram/README.md
@@ -12,7 +12,7 @@ This IP supports supports 4 open active rows (one per bank).
 
 Verified under simulation against a couple of SDRAM models and on the miniSpartan6+ board which features the AS4C16M16S.
 
-The supplied testbench works with the free version Modelsim.
+The supplied testbench works with the free version of Modelsim.
 
 ##### Configuration
 * SDRAM_MHZ - Clock speed (verified with 50MHz & 100MHz)
@@ -25,6 +25,6 @@ The supplied testbench works with the free version Modelsim.
 
 With the default configuration...
 
-* the design contains 191 flops.
+* the design contains 184 flops.
 * synthesizes to > 160MHz on Xilinx Spartan 6 LX9 (speed -3)
 * can hit up-to 92% of maximum bus rate for sequential accesses taking into account row open/close and refreshes.
diff --git a/sdram/rtl/sdram.v b/sdram/rtl/sdram.v
@@ -417,7 +417,7 @@ else
 //-----------------------------------------------------------------
 // Refresh counter
 //-----------------------------------------------------------------
-localparam REFRESH_CNT_W = 24;
+localparam REFRESH_CNT_W = 17;
 
 reg [REFRESH_CNT_W-1:0] refresh_timer_q;
 always @ (posedge rst_i or posedge clk_i)