Skip to content

Commit

Permalink
Merge pull request black-parrot#539 from Songchun-Li/me_dev_fill_evict
Browse files Browse the repository at this point in the history 
Partial Fill / Eviction Cache Service Interface Modification
  • Loading branch information
@muwyse
muwyse authored Jun 17, 2020
2 parents 42cadcd + 5b606e1 commit 59f0e11
Show file tree
Hide file tree
Showing 29 changed files with 859 additions and 532 deletions.
228 changes: 131 additions & 97 deletions bp_be/src/v/bp_be_mem/bp_be_dcache/bp_be_dcache.v
View file

Large diffs are not rendered by default.

20 changes: 10 additions & 10 deletions bp_be/src/v/bp_be_mem/bp_be_mem_top.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,23 +16,22 @@ module bp_be_mem_top
import bp_be_dcache_pkg::*;
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_cache_service_if_widths(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache)
`declare_bp_cache_service_if_widths(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache_fill_width_p, dcache)

// Generated parameters
// D$
, localparam block_size_in_words_lp = dcache_assoc_p // Due to cache interleaving scheme
, localparam bank_width_lp = dcache_block_width_p / dcache_assoc_p
, localparam num_dwords_per_bank_lp = bank_width_lp / dword_width_p
, localparam data_mem_mask_width_lp = (bank_width_lp >> 3) // Byte mask
, localparam bypass_data_mask_width_lp = (dword_width_p >> 3)
, localparam byte_offset_width_lp = `BSG_SAFE_CLOG2(bank_width_lp >> 3)
, localparam word_offset_width_lp = `BSG_SAFE_CLOG2(block_size_in_words_lp)
, localparam block_offset_width_lp = (word_offset_width_lp + byte_offset_width_lp)
, localparam bank_offset_width_lp = `BSG_SAFE_CLOG2(dcache_assoc_p)
, localparam block_offset_width_lp = (bank_offset_width_lp + byte_offset_width_lp)
, localparam index_width_lp = `BSG_SAFE_CLOG2(dcache_sets_p)
, localparam page_offset_width_lp = (block_offset_width_lp + index_width_lp)
, localparam way_id_width_lp=`BSG_SAFE_CLOG2(dcache_assoc_p)
, localparam stat_info_width_lp = `bp_cache_stat_info_width(dcache_assoc_p)

, localparam stat_info_width_lp = `bp_cache_stat_info_width(dcache_assoc_p)

, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p)

Expand Down Expand Up @@ -81,6 +80,7 @@ module bp_be_mem_top
, output logic cache_req_metadata_v_o

, input cache_req_complete_i
, input cache_req_critical_i

// data_mem
, input data_mem_pkt_v_i
Expand Down Expand Up @@ -119,7 +119,7 @@ module bp_be_mem_top
// Not sure if this is right.
`declare_bp_be_mmu_structs(vaddr_width_p, ptag_width_p, dcache_sets_p, dcache_block_width_p/8)
`declare_bp_be_dcache_pkt_s(page_offset_width_lp, dword_width_p);
`declare_bp_cache_service_if(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache);
`declare_bp_cache_service_if(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache_fill_width_p, dcache);
bp_dcache_req_s cache_req_cast_o;

assign cache_req_o = cache_req_cast_o;
Expand Down Expand Up @@ -361,7 +361,7 @@ bp_be_ptw
,.dcache_v_o(ptw_dcache_v)
,.dcache_pkt_o(ptw_dcache_pkt)
,.dcache_ptag_o(ptw_dcache_ptag)
,.dcache_rdy_i(dcache_ready_lo)
,.dcache_rdy_i(dcache_ready_lo)
,.dcache_miss_i(dcache_miss_lo)
);

Expand Down Expand Up @@ -394,6 +394,7 @@ bp_be_dcache
// D$-LCE Interface
,.dcache_miss_o(dcache_miss_lo)
,.cache_req_complete_i(cache_req_complete_i)
,.cache_req_critical_i(cache_req_critical_i)
,.cache_req_o(cache_req_cast_o)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_ready_i(cache_req_ready_i)
Expand Down Expand Up @@ -527,4 +528,3 @@ always_ff @(negedge clk_i)
// synopsys translate_on
//
endmodule

29 changes: 15 additions & 14 deletions bp_be/src/v/bp_be_top.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
*
* Name:
* bp_be_top.v
*
*
*/


Expand All @@ -16,11 +16,11 @@ module bp_be_top
#(parameter bp_params_e bp_params_p = e_bp_inv_cfg
`declare_bp_proc_params(bp_params_p)
`declare_bp_fe_be_if_widths(vaddr_width_p, paddr_width_p, asid_width_p, branch_metadata_fwd_width_p)
`declare_bp_cache_service_if_widths(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache)
`declare_bp_cache_service_if_widths(paddr_width_p, ptag_width_p, dcache_sets_p, dcache_assoc_p, dword_width_p, dcache_block_width_p, dcache_fill_width_p, dcache)

// Default parameters
// Default parameters
, localparam cfg_bus_width_lp = `bp_cfg_bus_width(vaddr_width_p, core_id_width_p, cce_id_width_p, lce_id_width_p, cce_pc_width_p, cce_instr_width_p)

// VM parameters
, localparam tlb_entry_width_lp = `bp_pte_entry_leaf_width(paddr_width_p)
, localparam stat_info_width_lp = `bp_cache_stat_info_width(dcache_assoc_p)
Expand Down Expand Up @@ -58,7 +58,8 @@ module bp_be_top
, output logic cache_req_metadata_v_o

, input cache_req_complete_i

, input cache_req_critical_i

// data_mem
, input data_mem_pkt_v_i
, input [dcache_data_mem_pkt_width_lp-1:0] data_mem_pkt_i
Expand Down Expand Up @@ -138,7 +139,7 @@ logic wb_pkt_v;

logic flush;
// Module instantiations
bp_be_checker_top
bp_be_checker_top
#(.bp_params_p(bp_params_p))
be_checker
(.clk_i(clk_i)
Expand Down Expand Up @@ -182,7 +183,7 @@ bp_be_checker_top
,.wb_pkt_i(wb_pkt)
);

bp_be_calculator_top
bp_be_calculator_top
#(.bp_params_p(bp_params_p))
be_calculator
(.clk_i(clk_i)
Expand All @@ -202,9 +203,9 @@ bp_be_calculator_top
,.csr_cmd_v_o(csr_cmd_v)
,.csr_cmd_ready_i(csr_cmd_rdy)

,.mem_resp_i(mem_resp)
,.mem_resp_i(mem_resp)
,.mem_resp_v_i(mem_resp_v)
,.mem_resp_ready_o(mem_resp_rdy)
,.mem_resp_ready_o(mem_resp_rdy)

,.commit_pkt_o(commit_pkt)
,.wb_pkt_o(wb_pkt)
Expand Down Expand Up @@ -233,19 +234,20 @@ bp_be_mem_top
,.mem_resp_o(mem_resp)
,.mem_resp_v_o(mem_resp_v)
,.mem_resp_ready_i(mem_resp_rdy)

,.itlb_fill_v_o(itlb_fill_v)
,.itlb_fill_vaddr_o(itlb_fill_vaddr)
,.itlb_fill_entry_o(itlb_fill_entry)

,.cache_req_complete_i(cache_req_complete_i)

,.cache_req_complete_i(cache_req_complete_i)
,.cache_req_critical_i(cache_req_critical_i)

,.cache_req_o(cache_req_o)
,.cache_req_metadata_o(cache_req_metadata_o)
,.cache_req_v_o(cache_req_v_o)
,.cache_req_ready_i(cache_req_ready_i)
,.cache_req_metadata_v_o(cache_req_metadata_v_o)

,.data_mem_pkt_v_i(data_mem_pkt_v_i)
,.data_mem_pkt_i(data_mem_pkt_i)
,.data_mem_o(data_mem_o)
Expand Down Expand Up @@ -273,4 +275,3 @@ bp_be_mem_top
);

endmodule

5 changes: 3 additions & 2 deletions bp_be/syn/flist.vcs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -111,6 +111,7 @@ $BASEJUMP_STL_DIR/bsg_misc/bsg_dff_chain.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_en.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_dff_reset_set_clear.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_edge_detect.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_encode_one_hot.v
$BASEJUMP_STL_DIR/bsg_misc/bsg_expand_bitmask.v
Expand Down Expand Up @@ -154,8 +155,8 @@ $BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_in.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_adapter_out.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_decoder_dor.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_input_control.v
$BASEJUMP_STL_DIR/bsg_noc/bsg_wormhole_router_output_control.v
# Common files
$BP_COMMON_DIR/src/v/bsg_fifo_1r1w_rolly.v
$BP_COMMON_DIR/src/v/bp_pma.v
Expand Down
39 changes: 20 additions & 19 deletions bp_be/test/tb/bp_be_dcache/testbench.v
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
* testbench.v
*
*/

module testbench
import bp_common_pkg::*;
import bp_common_aviary_pkg::*;
Expand Down Expand Up @@ -49,7 +49,7 @@ module testbench
, localparam ptag_width_lp = (paddr_width_p - page_offset_width_lp)
, localparam dcache_pkt_width_lp = `bp_be_dcache_pkt_width(page_offset_width_p, dword_width_p)
, localparam trace_replay_data_width_lp = ptag_width_lp + dcache_pkt_width_lp + 1 // The 1 extra bit is for uncached accesses
, localparam trace_rom_addr_width_lp = 8
, localparam trace_rom_addr_width_lp = 8

, localparam yumi_min_delay_lp = 0
, localparam yumi_max_delay_lp = 15
Expand All @@ -68,7 +68,7 @@ module testbench
logic mem_cmd_v_lo, mem_resp_v_lo;
logic mem_cmd_ready_lo, mem_resp_yumi_lo;
logic [cce_mem_msg_width_lp-1:0] mem_cmd_lo, mem_resp_lo;

logic [trace_replay_data_width_lp-1:0] trace_data_lo;
logic trace_v_lo;
logic dut_ready_lo;
Expand Down Expand Up @@ -152,7 +152,7 @@ module testbench
(.addr_i(trace_rom_addr_lo)
,.data_o(trace_rom_data_li)
);

assign dcache_pkt_li = trace_data_lo[0+:dcache_pkt_width_lp];
assign ptag_li = trace_data_lo[dcache_pkt_width_lp+:ptag_width_lp];
assign uncached_li = trace_data_lo[(dcache_pkt_width_lp+ptag_width_lp)+:1];
Expand All @@ -179,10 +179,10 @@ module testbench
// We need an 8 FIFO because we might be receiving all data at once rather
// than receive data at regular intervals. This is possible a side effect of
// our testing strategy. Open for debate.
bsg_fifo_1r1w_small
bsg_fifo_1r1w_small
#(.width_p(dword_width_p)
,.els_p(8))
output_fifo
output_fifo
(.clk_i(clk_i)
,.reset_i(reset_i)

Expand All @@ -205,7 +205,7 @@ module testbench
wrapper
(.clk_i(clk_i)
,.reset_i(reset_i)

,.cfg_bus_i(cfg_bus_li)

,.dcache_pkt_i(dcache_pkt_li)
Expand All @@ -218,7 +218,7 @@ module testbench
,.ptag_i(ptag_li)

,.uncached_i(uncached_li)

,.mem_resp_v_i(mem_resp_v_lo)
,.mem_resp_i(mem_resp_lo)
,.mem_resp_yumi_o(mem_resp_yumi_lo)
Expand All @@ -236,12 +236,12 @@ module testbench
,.mem_zero_p(mem_zero_p)
,.mem_file_p(mem_file_p)
,.mem_offset_p(mem_offset_p)

,.use_max_latency_p(use_max_latency_p)
,.use_random_latency_p(use_random_latency_p)
,.use_dramsim2_latency_p(use_dramsim2_latency_p)
,.max_latency_p(max_latency_p)

,.dram_clock_period_in_ps_p(dram_clock_period_in_ps_p)
,.dram_cfg_p(dram_cfg_p)
,.dram_sys_cfg_p(dram_sys_cfg_p)
Expand All @@ -250,11 +250,11 @@ module testbench
mem
(.clk_i(clk_i)
,.reset_i(reset_i)

,.mem_cmd_i(mem_cmd_lo)
,.mem_cmd_v_i(mem_cmd_v_lo)
,.mem_cmd_ready_o(mem_cmd_ready_lo)

,.mem_resp_o(mem_resp_lo)
,.mem_resp_v_o(mem_resp_v_lo)
,.mem_resp_yumi_i(mem_resp_yumi_lo)
Expand All @@ -267,11 +267,12 @@ module testbench
,.sets_p(dcache_sets_p)
,.assoc_p(dcache_assoc_p)
,.block_width_p(dcache_block_width_p)
,.fill_width_p(dcache_fill_width_p)
,.trace_file_p("dcache"))
dcache_tracer
(.clk_i(clk_i & (testbench.dcache_trace_p == 1))
,.reset_i(reset_i)

,.freeze_i(cfg_bus_cast_i.freeze)
,.mhartid_i(cfg_bus_cast_i.core_id)

Expand Down Expand Up @@ -315,10 +316,10 @@ module testbench
bp_cce_tracer
(.clk_i(clk_i & (testbench.cce_trace_p == 1))
,.reset_i(reset_i)

,.freeze_i(cfg_bus_cast_i.freeze)
,.cce_id_i(cfg_bus_cast_i.cce_id)

// To CCE
,.lce_req_i(lce_req_i)
,.lce_req_v_i(lce_req_v_i)
Expand All @@ -327,17 +328,17 @@ module testbench
,.lce_resp_i(lce_resp_i)
,.lce_resp_v_i(lce_resp_v_i)
,.lce_resp_yumi_i(lce_resp_yumi_o)

// From CCE
,.lce_cmd_i(lce_cmd_o)
,.lce_cmd_v_i(lce_cmd_v_o)
,.lce_cmd_ready_i(lce_cmd_ready_i)

// To CCE
,.mem_resp_i(mem_resp_i)
,.mem_resp_v_i(mem_resp_v_i)
,.mem_resp_yumi_i(mem_resp_yumi_o)

// From CCE
,.mem_cmd_i(mem_cmd_o)
,.mem_cmd_v_i(mem_cmd_v_o)
Expand All @@ -359,7 +360,7 @@ module testbench
,.mem_resp_v_i(mem_resp_v_lo)
,.mem_resp_yumi_i(mem_resp_yumi_lo)
);

// Assertions
if(uce_p == 0 && l1_writethrough_p == 1)
$error("Writethrough cache with CCE not yet supported");
Expand Down
Loading

0 comments on commit 59f0e11

Please sign in to comment.