#mshr, #wbuffers in simout; cpu_read/write_hits/misses stats

adarshpatil · Feb 10, 2017 · 17d2617 · 17d2617
1 parent 8a4b253
commit 17d2617
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Showing 2 changed files with 35 additions and 0 deletions.
diff --git a/gem5/src/mem/dramcache_ctrl.cc b/gem5/src/mem/dramcache_ctrl.cc
@@ -83,6 +83,7 @@ DRAMCacheCtrl::DRAMCacheCtrl (const DRAMCacheCtrlParams* p) :
 	inform("DRAMCache writeLowThreshold %d writeHighThreshold %d\n",
 			writeLowThreshold, writeHighThreshold);
 	inform("DRAMCache address mapping %d, page mgmt %d", addrMapping, pageMgmt);
+	inform("DRAMCache mshrs %d, writebuffers %d", p->mshrs , p->write_buffers);
 }
 
 void
@@ -181,10 +182,17 @@ DRAMCacheCtrl::doCacheLookup (PacketPtr pkt)
 		}
 
 		if (pkt->isRead ())
+		{
 			dramCache_read_hits++;
+			if (pkt->req->contextId () != 31)
+				dramCache_cpu_read_hits++;
+		}
+
 		else
 		{
 			dramCache_write_hits++;
+			if (pkt->req->contextId () != 31)
+				dramCache_cpu_write_hits++;
 
 			if (!set[cacheSet].dirty && isGPUOwned[cacheSet]) // write to a clean line & GPU owned
 			{
@@ -283,10 +291,16 @@ DRAMCacheCtrl::doCacheLookup (PacketPtr pkt)
 		// adding to MSHR will be done elsewhere
 
 		if (pkt->isRead ())
+		{
 			dramCache_read_misses++;
+			if (pkt->req->contextId () != 31)
+				dramCache_cpu_read_misses++;
+		}
 		else
 		{
 			dramCache_write_misses++;
+			if (pkt->req->contextId () != 31)
+				dramCache_cpu_write_misses++;
 			// gpu requesting a write and existing line was clean and not GPU owned
 			if (pkt->req->contextId () == 31 &&
 					!(set[cacheSet].dirty && isGPUOwned[cacheSet]) &&
@@ -2231,6 +2245,22 @@ DRAMCacheCtrl::regStats ()
 	.name (name () + ".dramCache_write_misses")
 	.desc ("Number of write misses in dramcache");
 
+	dramCache_cpu_read_hits
+		.name (name () + ".dramCache_cpu_read_hits")
+		.desc ("Number of read hits in dramcache");
+
+	dramCache_read_misses
+		.name (name () + ".dramCache_cpu_read_misses")
+		.desc ("Number of read misses in dramcache");
+
+	dramCache_write_hits
+		.name (name () + ".dramCache_cpu_write_hits")
+		.desc ("Number of write hits in dramcache");
+
+	dramCache_write_misses
+	    .name (name () + ".dramCache_cpu_write_misses")
+	    .desc ("Number of write misses in dramcache");
+
 	dramCache_evicts
 		.name (name () + ".dramCache_evicts")
 		.desc ("Number of evictions from dramcache");

diff --git a/gem5/src/mem/dramcache_ctrl.hh b/gem5/src/mem/dramcache_ctrl.hh
@@ -248,6 +248,11 @@ class DRAMCacheCtrl : public DRAMCtrl
 	Stats::Scalar dramCache_read_misses;
 	Stats::Scalar dramCache_write_hits;
 	Stats::Scalar dramCache_write_misses;
+	Stats::Scalar dramCache_cpu_read_hits;
+	Stats::Scalar dramCache_cpu_read_misses;
+	Stats::Scalar dramCache_cpu_write_hits;
+	Stats::Scalar dramCache_cpu_write_misses;
+
 	Stats::Scalar dramCache_evicts;
 	Stats::Scalar dramCache_write_backs;
 	Stats::Scalar dramCache_write_backs_on_read;