stats - pam_returned_before_access, gpu_replaced_gpu

adarshpatil · Feb 6, 2017 · 64cb169 · 64cb169
1 parent e8e3ea9
commit 64cb169
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Showing 2 changed files with 19 additions and 0 deletions.
diff --git a/gem5/src/mem/dramcache_ctrl.cc b/gem5/src/mem/dramcache_ctrl.cc
@@ -238,6 +238,7 @@ DRAMCacheCtrl::doCacheLookup (PacketPtr pkt)
 				}
 				if (isGPUOwned[cacheSet]) //set occupied by GPU line
 				{
+					dramCache_gpu_replaced_gpu++;
 					// gpu req replacing gpu line
 					if (set[cacheSet].dirty)  // GPU dirty line will be evicted
 						total_gpu_dirty_lines--;
@@ -1302,6 +1303,7 @@ DRAMCacheCtrl::addToReadQueue(PacketPtr pkt, unsigned int pktCount)
 		{
 			DPRINTF(DRAMCache,"sending PAM request for addr %d contextId %d\n",
 					pkt->getAddr(), pkt->req->contextId());
+			dramCache_pam_requests++;
 			// predicted as miss do PAM
 			// allocate in PAMQueue
 			// create an entry in MSHR, which will send a request to memory
@@ -1730,6 +1732,7 @@ DRAMCacheCtrl::recvTimingResp (PacketPtr pkt)
 		// found in PAM Queue
 		if (pr->isHit == -1)
 		{
+			dramCache_pam_returned_before_access++;
 			// DRAMCache hasn't done access so we dont know hit or miss
 			// we put the data returned from this packet, that came from DRAM
 			// into the first target of the MSHR for use incase of a miss
@@ -2252,6 +2255,10 @@ DRAMCacheCtrl::regStats ()
 		.name (name () + ".dramCache_cpu_replaced_gpu")
 		.desc ("Number of times cpu replaced gpu line");
 
+	dramCache_gpu_replaced_gpu
+	    .name (name () + ".dramCache_gpu_replaced_gpu")
+	    .desc ("Number of times gpu replaced gpu line");
+
 	switched_to_gpu_line
 		.name (name () + ".switched_to_gpu_line")
 		.desc ("Number of times CPU line became GPU line in cache ");
@@ -2300,6 +2307,14 @@ DRAMCacheCtrl::regStats ()
 		.name ( name() + ".dramCache_incorrect_pred")
 		.desc("Number of incorrect predictions");
 
+	dramCache_pam_requests
+	    .name ( name() + ".dramCache_pam_requests")
+	    .desc("Number of pam requests sent");
+
+	dramCache_pam_returned_before_access
+	    .name ( name() + ".dramCache_pam_returned_before_access")
+	    .desc("times pam returned before access in cache completed");
+
 	dramCache_noncpu0_cpu_accesses
 		.name (name () + ".dramCache_noncpu0_cpu_accesses")
 		.desc ("Number of non cpu0 accesses");

diff --git a/gem5/src/mem/dramcache_ctrl.hh b/gem5/src/mem/dramcache_ctrl.hh
@@ -254,6 +254,7 @@ class DRAMCacheCtrl : public DRAMCtrl
 	Stats::Scalar dramCache_writes_to_dirty_lines;
 	Stats::Scalar dramCache_gpu_replaced_cpu;
 	Stats::Scalar dramCache_cpu_replaced_gpu;
+	Stats::Scalar dramCache_gpu_replaced_gpu;
 	Stats::Scalar switched_to_gpu_line; // CPU lines that became GPU lines in cache
 	Stats::Scalar switched_to_cpu_line; // GPU lines that became CPU lines in cache
 	Stats::Scalar dramCache_cpu_hits;   // hits for CPU req
@@ -273,6 +274,9 @@ class DRAMCacheCtrl : public DRAMCtrl
 	Stats::Scalar dramCache_total_pred; // number of predictions made
 	Stats::Scalar dramCache_incorrect_pred; // number of miss predictions by predictor
 
+	Stats::Scalar dramCache_pam_requests; // number of times pam request sent
+	Stats::Scalar dramCache_pam_returned_before_access;
+
 	Stats::Scalar dramCache_noncpu0_cpu_accesses;
 	Stats::Scalar dramCache_noncpu0_cpu_hits;
 	Stats::Formula dramCache_noncpu0_cpu_hit_rate;