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Merge branch 'spi-5.3' into spi-next
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broonie committed Jul 4, 2019
2 parents 2337ff4 + 8cc7720 commit 106dbe2
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20 changes: 15 additions & 5 deletions Documentation/devicetree/bindings/mfd/atmel-usart.txt
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Expand Up @@ -17,17 +17,24 @@ Required properties for USART in SPI mode:
- cs-gpios: chipselects (internal cs not supported)
- atmel,usart-mode : Must be <AT91_USART_MODE_SPI> (found in dt-bindings/mfd/at91-usart.h)

Optional properties in serial and SPI mode:
- dma bindings for dma transfer:
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
memory peripheral interface and USART DMA channel ID, FIFO configuration.
The order of DMA channels is fixed. The first DMA channel must be TX
associated channel and the second one must be RX associated channel.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "tx" for TX channel.
"rx" for RX channel.
The order of dma-names is also fixed. The first name must be "tx"
and the second one must be "rx" as in the examples below.

Optional properties in serial mode:
- atmel,use-dma-rx: use of PDC or DMA for receiving data
- atmel,use-dma-tx: use of PDC or DMA for transmitting data
- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively.
It will use specified PIO instead of the peripheral function pin for the USART feature.
If unsure, don't specify this property.
- add dma bindings for dma transfer:
- dmas: DMA specifier, consisting of a phandle to DMA controller node,
memory peripheral interface and USART DMA channel ID, FIFO configuration.
Refer to dma.txt and atmel-dma.txt for details.
- dma-names: "rx" for RX channel, "tx" for TX channel.
- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO
capable USARTs.
- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt
Expand Down Expand Up @@ -81,5 +88,8 @@ Example:
interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
clocks = <&usart0_clk>;
clock-names = "usart";
dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>,
<&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
dma-names = "tx", "rx";
cs-gpios = <&pioB 3 0>;
};
86 changes: 86 additions & 0 deletions Documentation/devicetree/bindings/spi/allwinner,sun4i-a10-spi.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/allwinner,sun4i-a10-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A10 SPI Controller Device Tree Bindings

allOf:
- $ref: "spi-controller.yaml"

maintainers:
- Chen-Yu Tsai <[email protected]>
- Maxime Ripard <[email protected]>

properties:
"#address-cells": true
"#size-cells": true

compatible:
const: allwinner,sun4i-a10-spi

reg:
maxItems: 1

interrupts:
maxItems: 1

clocks:
items:
- description: Bus Clock
- description: Module Clock

clock-names:
items:
- const: ahb
- const: mod

dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel

dma-names:
items:
- const: rx
- const: tx

num-cs: true

patternProperties:
"^.*@[0-9a-f]+":
properties:
reg:
items:
minimum: 0
maximum: 4

spi-rx-bus-width:
const: 1

spi-tx-bus-width:
const: 1

required:
- compatible
- reg
- interrupts
- clocks
- clock-names

additionalProperties: false

examples:
- |
spi1: spi@1c06000 {
compatible = "allwinner,sun4i-a10-spi";
reg = <0x01c06000 0x1000>;
interrupts = <11>;
clocks = <&ahb_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
#address-cells = <1>;
#size-cells = <0>;
};
...
106 changes: 106 additions & 0 deletions Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml
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# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/spi/allwinner,sun6i-a31-spi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Allwinner A31 SPI Controller Device Tree Bindings

allOf:
- $ref: "spi-controller.yaml"

maintainers:
- Chen-Yu Tsai <[email protected]>
- Maxime Ripard <[email protected]>

properties:
"#address-cells": true
"#size-cells": true

compatible:
enum:
- allwinner,sun6i-a31-spi
- allwinner,sun8i-h3-spi

reg:
maxItems: 1

interrupts:
maxItems: 1

clocks:
items:
- description: Bus Clock
- description: Module Clock

clock-names:
items:
- const: ahb
- const: mod

resets:
maxItems: 1

dmas:
items:
- description: RX DMA Channel
- description: TX DMA Channel

dma-names:
items:
- const: rx
- const: tx

num-cs: true

patternProperties:
"^.*@[0-9a-f]+":
properties:
reg:
items:
minimum: 0
maximum: 4

spi-rx-bus-width:
const: 1

spi-tx-bus-width:
const: 1

required:
- compatible
- reg
- interrupts
- clocks
- clock-names

additionalProperties: false

examples:
- |
spi1: spi@1c69000 {
compatible = "allwinner,sun6i-a31-spi";
reg = <0x01c69000 0x1000>;
interrupts = <0 66 4>;
clocks = <&ahb1_gates 21>, <&spi1_clk>;
clock-names = "ahb", "mod";
resets = <&ahb1_rst 21>;
#address-cells = <1>;
#size-cells = <0>;
};
- |
spi0: spi@1c68000 {
compatible = "allwinner,sun8i-h3-spi";
reg = <0x01c68000 0x1000>;
interrupts = <0 65 4>;
clocks = <&ccu 30>, <&ccu 82>;
clock-names = "ahb", "mod";
dmas = <&dma 23>, <&dma 23>;
dma-names = "rx", "tx";
resets = <&ccu 15>;
#address-cells = <1>;
#size-cells = <0>;
};
...
112 changes: 1 addition & 111 deletions Documentation/devicetree/bindings/spi/spi-bus.txt
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SPI (Serial Peripheral Interface) busses

SPI busses can be described with a node for the SPI controller device
and a set of child nodes for each SPI slave on the bus. The system's SPI
controller may be described for use in SPI master mode or in SPI slave mode,
but not for both at the same time.

The SPI controller node requires the following properties:
- compatible - Name of SPI bus controller following generic names
recommended practice.

In master mode, the SPI controller node requires the following additional
properties:
- #address-cells - number of cells required to define a chip select
address on the SPI bus.
- #size-cells - should be zero.

In slave mode, the SPI controller node requires one additional property:
- spi-slave - Empty property.

No other properties are required in the SPI bus node. It is assumed
that a driver for an SPI bus device will understand that it is an SPI bus.
However, the binding does not attempt to define the specific method for
assigning chip select numbers. Since SPI chip select configuration is
flexible and non-standardized, it is left out of this binding with the
assumption that board specific platform code will be used to manage
chip selects. Individual drivers can define additional properties to
support describing the chip select layout.

Optional properties (master mode only):
- cs-gpios - gpios chip select.
- num-cs - total number of chipselects.

If cs-gpios is used the number of chip selects will be increased automatically
with max(cs-gpios > hw cs).

So if for example the controller has 2 CS lines, and the cs-gpios
property looks like this:

cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;

Then it should be configured so that num_chipselect = 4 with the
following mapping:

cs0 : &gpio1 0 0
cs1 : native
cs2 : &gpio1 1 0
cs3 : &gpio1 2 0


SPI slave nodes must be children of the SPI controller node.

In master mode, one or more slave nodes (up to the number of chip selects) can
be present. Required properties are:
- compatible - Name of SPI device following generic names recommended
practice.
- reg - Chip select address of device.
- spi-max-frequency - Maximum SPI clocking speed of device in Hz.

In slave mode, the (single) slave node is optional.
If present, it must be called "slave". Required properties are:
- compatible - Name of SPI device following generic names recommended
practice.

All slave nodes can contain the following optional properties:
- spi-cpol - Empty property indicating device requires inverse clock
polarity (CPOL) mode.
- spi-cpha - Empty property indicating device requires shifted clock
phase (CPHA) mode.
- spi-cs-high - Empty property indicating device requires chip select
active high.
- spi-3wire - Empty property indicating device requires 3-wire mode.
- spi-lsb-first - Empty property indicating device requires LSB first mode.
- spi-tx-bus-width - The bus width (number of data wires) that is used for MOSI.
Defaults to 1 if not present.
- spi-rx-bus-width - The bus width (number of data wires) that is used for MISO.
Defaults to 1 if not present.
- spi-rx-delay-us - Microsecond delay after a read transfer.
- spi-tx-delay-us - Microsecond delay after a write transfer.

Some SPI controllers and devices support Dual and Quad SPI transfer mode.
It allows data in the SPI system to be transferred using 2 wires (DUAL) or 4
wires (QUAD).
Now the value that spi-tx-bus-width and spi-rx-bus-width can receive is
only 1 (SINGLE), 2 (DUAL) and 4 (QUAD).
Dual/Quad mode is not allowed when 3-wire mode is used.

If a gpio chipselect is used for the SPI slave the gpio number will be passed
via the SPI master node cs-gpios property.

SPI example for an MPC5200 SPI bus:
spi@f00 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
reg = <0xf00 0x20>;
interrupts = <2 13 0 2 14 0>;
interrupt-parent = <&mpc5200_pic>;

ethernet-switch@0 {
compatible = "micrel,ks8995m";
spi-max-frequency = <1000000>;
reg = <0>;
};

codec@1 {
compatible = "ti,tlv320aic26";
spi-max-frequency = <100000>;
reg = <1>;
};
};
This file has moved to spi-controller.yaml.
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