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Fixed line endings
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LarsAsplund committed Jun 1, 2019
1 parent 85f1607 commit 82f5d55
Showing 424 changed files with 79,464 additions and 79,435 deletions.
29 changes: 29 additions & 0 deletions .gitattributes
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2 changes: 1 addition & 1 deletion docs/release_notes/0.52.0.rst
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Added function to get the number of messages missed by a com package actor.
Added function to get the number of messages missed by a com package actor.
6 changes: 3 additions & 3 deletions docs/release_notes/0.53.0.rst
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@@ -1,3 +1,3 @@
- ``add_source_files`` accepts a list of files
- Added ``-f/--files`` command line flag to list all files in compile order
- Verilog parser improvements in robustness and error messages.
- ``add_source_files`` accepts a list of files
- Added ``-f/--files`` command line flag to list all files in compile order
- Verilog parser improvements in robustness and error messages.
4 changes: 2 additions & 2 deletions docs/release_notes/0.54.0.rst
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@@ -1,2 +1,2 @@
- Adds support for Verilog preprocessor ifdef/ifndef/elsif/else/endif
- Fixes regression in modelsim persistent mode. Makes many short tests faster.
- Adds support for Verilog preprocessor ifdef/ifndef/elsif/else/endif
- Fixes regression in modelsim persistent mode. Makes many short tests faster.
2 changes: 1 addition & 1 deletion docs/release_notes/0.56.0.rst
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- Verilog preprocessing of resetall / undefineall / undef
- Verilog preprocessing of resetall / undefineall / undef
4 changes: 2 additions & 2 deletions docs/release_notes/0.57.0.rst
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- Adds ``include_dirs`` argument also to ``Library`` add_source_file(s)
- Ignores more builtin Verilog preprocessor directives.
- Adds ``include_dirs`` argument also to ``Library`` add_source_file(s)
- Ignores more builtin Verilog preprocessor directives.
4 changes: 2 additions & 2 deletions docs/release_notes/0.58.0.rst
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@@ -1,2 +1,2 @@
- Parsing Verilog package references. :vunit_issue:`119`
- Added ``scan_tests_from_file`` public method. :vunit_issue:`121`.
- Parsing Verilog package references. :vunit_issue:`119`
- Added ``scan_tests_from_file`` public method. :vunit_issue:`121`.
6 changes: 3 additions & 3 deletions docs/release_notes/0.59.0.rst
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@@ -1,3 +1,3 @@
- Covered a miss in circular dependency detection.
- Added detection of circular includes and macro expansions in verilog preprocessing.
- Added caching of verilog parse results for significant speed when running run.py more than once.
- Covered a miss in circular dependency detection.
- Added detection of circular includes and macro expansions in verilog preprocessing.
- Added caching of verilog parse results for significant speed when running run.py more than once.
6 changes: 3 additions & 3 deletions docs/release_notes/0.60.0.rst
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@@ -1,3 +1,3 @@
- Better error messages when there are circular dependencies.
- Added ``defines`` argument to add_source_file(s) :vunit_issue:`126`
- Made ``--files`` deterministic with Python 3 :vunit_issue:`116`
- Better error messages when there are circular dependencies.
- Added ``defines`` argument to add_source_file(s) :vunit_issue:`126`
- Made ``--files`` deterministic with Python 3 :vunit_issue:`116`
2 changes: 1 addition & 1 deletion docs/release_notes/0.60.1.rst
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- Avoids crash with errors in Verilog defines from Python string in run.py
- Avoids crash with errors in Verilog defines from Python string in run.py
6 changes: 3 additions & 3 deletions docs/release_notes/0.61.0.rst
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- Adds ``.all`` suffix to test benches with no test to better align with XUnit architecture.
- Enables better hierarchical JUnit XML report view in Jenkins.
- Fixes :vunit_issue:`129`.
- Adds ``.all`` suffix to test benches with no test to better align with XUnit architecture.
- Enables better hierarchical JUnit XML report view in Jenkins.
- Fixes :vunit_issue:`129`.
4 changes: 2 additions & 2 deletions docs/release_notes/0.62.0.rst
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- Early runtime error when gtkwave is missing. Closes :vunit_issue:`137`
- Added add_compile_option. Closes :vunit_issue:`118`
- Early runtime error when gtkwave is missing. Closes :vunit_issue:`137`
- Added add_compile_option. Closes :vunit_issue:`118`
2 changes: 1 addition & 1 deletion docs/release_notes/0.63.0.rst
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- Update test scanner pattern to be based on ``runner_cfg``. :vunit_issue:`138`
- Update test scanner pattern to be based on ``runner_cfg``. :vunit_issue:`138`
4 changes: 2 additions & 2 deletions docs/release_notes/0.64.0.rst
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- Added python version check. Closes :vunit_issue:`141`.
- Not adding .all suffix when there are named configurations
- Added python version check. Closes :vunit_issue:`141`.
- Not adding .all suffix when there are named configurations
18 changes: 9 additions & 9 deletions docs/release_notes/0.65.0.rst
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- Added sim and compile options to set rivierapro/activehdl flags. :vunit_issue:`143`.
- Removed builtin ``-dbg`` flag to vcom for aldec tools. Use set_compile_option instead to set it yourself.
- Fixed a bug with custom relative output_path.
- Documentation fixes & improvements.
- Update rivierapro and activehdl toolchain discovery. :vunit_issue:`148`.
- Added possibility to set ``VUNIT_<SIMULATOR_NAME>_PATH`` environment
variable to specify simulation executable path. :vunit_issue:`148`.
- Added ``-k/--keep-compiling`` flag. :vunit_issue:`140`.
- Added optional ``output_path`` argument to ``pre_config``. :vunit_issue:`146`.
- Added sim and compile options to set rivierapro/activehdl flags. :vunit_issue:`143`.
- Removed builtin ``-dbg`` flag to vcom for aldec tools. Use set_compile_option instead to set it yourself.
- Fixed a bug with custom relative output_path.
- Documentation fixes & improvements.
- Update rivierapro and activehdl toolchain discovery. :vunit_issue:`148`.
- Added possibility to set ``VUNIT_<SIMULATOR_NAME>_PATH`` environment
variable to specify simulation executable path. :vunit_issue:`148`.
- Added ``-k/--keep-compiling`` flag. :vunit_issue:`140`.
- Added optional ``output_path`` argument to ``pre_config``. :vunit_issue:`146`.
4 changes: 2 additions & 2 deletions docs/release_notes/0.66.0.rst
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@@ -1,2 +1,2 @@
- Fixed :vunit_issue:`109`, :vunit_issue:`141`, :vunit_issue:`153`, :vunit_issue:`155`.
- Fixed relative path for multiple drives on windows.
- Fixed :vunit_issue:`109`, :vunit_issue:`141`, :vunit_issue:`153`, :vunit_issue:`155`.
- Fixed relative path for multiple drives on windows.
32 changes: 16 additions & 16 deletions docs/release_notes/0.67.0.rst
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- A number of minor enhancements and bug fixes
- Added vunit_restart TCL procedure to ModelSim
- Print out remaining number of tests when pressing ctrl-c
- Updated OSVVM and made it a git submodule. Run

.. code-block:: console
git submodule update --init --recursive
after updating an existing Git repository or

.. code-block:: console
git clone --recursive https://github.com/VUnit/vunit.git
when creating a new clone to get the OSVVM subdirectory of VUnit populated. Doesn't affect installations made from PyPi
- A number of minor enhancements and bug fixes
- Added vunit_restart TCL procedure to ModelSim
- Print out remaining number of tests when pressing ctrl-c
- Updated OSVVM and made it a git submodule. Run

.. code-block:: console
git submodule update --init --recursive
after updating an existing Git repository or

.. code-block:: console
git clone --recursive https://github.com/VUnit/vunit.git
when creating a new clone to get the OSVVM subdirectory of VUnit populated. Doesn't affect installations made from PyPi
2 changes: 1 addition & 1 deletion docs/release_notes/0.68.0.rst
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Added check_equal for time and updated documentation.
Added check_equal for time and updated documentation.
2 changes: 1 addition & 1 deletion docs/release_notes/0.68.1.rst
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New version to fix broken PyPi upload
New version to fix broken PyPi upload
2 changes: 1 addition & 1 deletion docs/release_notes/0.69.0.rst
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Added check_equal for strings.
Added check_equal for strings.
6 changes: 3 additions & 3 deletions docs/release_notes/0.70.0.rst
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- Hashing test output_path to protect against special characters and long paths on Windows.
- Added ``.vo`` as recognized Verilog file ending.
- Enable setting vhdl_standard per file.
- Hashing test output_path to protect against special characters and long paths on Windows.
- Added ``.vo`` as recognized Verilog file ending.
- Enable setting vhdl_standard per file.
2 changes: 1 addition & 1 deletion docs/release_notes/0.71.0.rst
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- Improved location preprocessing control
- Improved location preprocessing control
12 changes: 6 additions & 6 deletions docs/release_notes/1.0.0.rst
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@@ -1,6 +1,6 @@
- Adds ActiveHDL custom simulation flags support
- Made library simulator flag argument deterministic and same as the order added to VUnit
- Added check_equal between std_logic_vector and natural for unsigned comparison
- Can now set vhdl_standard on an external library
- Added no_parse argument to add_source_files(s) to inhibit any dependency or test scanning
- Renamed public method depends_on to add_dependency_on
- Adds ActiveHDL custom simulation flags support
- Made library simulator flag argument deterministic and same as the order added to VUnit
- Added check_equal between std_logic_vector and natural for unsigned comparison
- Can now set vhdl_standard on an external library
- Added no_parse argument to add_source_files(s) to inhibit any dependency or test scanning
- Renamed public method depends_on to add_dependency_on
6 changes: 3 additions & 3 deletions docs/release_notes/1.1.1.rst
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@@ -1,3 +1,3 @@
- Adds vunit_restart and vunit_compile TCL commands for both ModelSim and RivieraPro
- Also support persistent simulator to save startup overhead for RivieraPro.
- Changes --new-vsim into -u/--unique-sim which also works for riviera
- Adds vunit_restart and vunit_compile TCL commands for both ModelSim and RivieraPro
- Also support persistent simulator to save startup overhead for RivieraPro.
- Changes --new-vsim into -u/--unique-sim which also works for riviera
2 changes: 1 addition & 1 deletion docs/release_notes/1.2.0.rst
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@@ -1 +1 @@
- Updated OSVVM submodule
- Updated OSVVM submodule
4 changes: 2 additions & 2 deletions docs/release_notes/1.3.0.rst
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@@ -1,2 +1,2 @@
- Added support for pass acknowledge messages for check subprograms.
- Made design unit duplication a warning instead of runtime error again.
- Added support for pass acknowledge messages for check subprograms.
- Made design unit duplication a warning instead of runtime error again.
2 changes: 1 addition & 1 deletion docs/release_notes/1.3.1.rst
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@@ -1 +1 @@
- Fixed compile errors with GHDL 0.33
- Fixed compile errors with GHDL 0.33
8 changes: 4 additions & 4 deletions docs/release_notes/1.4.0.rst
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@@ -1,4 +1,4 @@
- Removed bug when compiling Verilog with Active-HDL
- Updated array package
- Added support for simulation init script
- Added support for setting VHDL asserts stop level from run script
- Removed bug when compiling Verilog with Active-HDL
- Updated array package
- Added support for simulation init script
- Added support for setting VHDL asserts stop level from run script
78 changes: 39 additions & 39 deletions docs/release_notes/2.0.0.rst
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@@ -1,39 +1,39 @@

Public interface changes
~~~~~~~~~~~~~~~~~~~~~~~~

Some ``run.py`` scripts can be broken by this. Both ``set_generic``
and ``add_config`` works differently internally.

``set_generic`` and ``set_sim_option`` now only affects files added
before the call so reordering within the ``run.py`` can be needed.

``add_config`` on the test case level will no longer discard
configurations added on the test bench level. This affects users
mixing adding configurations on both test and test case level for the
same test bench. Adding a configuration on the test bench level is now
seen as a shorthand for adding the configuration to all test cases
within the test bench. Configurations are only held at the test case
level now. Before there could be configurations on multiple levels
where the most specific level ignored all others. I now recommend
writing a for loop over test_bench.get_tests() adding configurations
to each test individually, see the updated generate_tests example.

We have also forbidden to have configurations without name (""), this
is since the default configuration of all test cases has no name. The
``post_check`` and ``pre_config`` can now be set using
``set_pre_config`` also without using ``add_config`` removing the need
to add a single unnamed configuration and instead setting these in the
default configuration.

This internal restructuring has been made to allow a sane data model
of configurations where they are attached to test cases. This allows
us to expose configurations objects on the public API in the future
allowing users more control and visibility. The current behavior of
configurations is also better documented than it ever was.

I suggest reading the section on :ref:`configurations <configurations>` in the docs.

- Replace ``disable_ieee_warnings`` and ``set_pli`` with corresponding simulation options.
- Adds ``--version`` flag
- Added ``--gui`` flag for GHDL to open gtkwave. Also allows saving waveform without opening gui with ``--gtkwave-fmt`` flag.

Public interface changes
~~~~~~~~~~~~~~~~~~~~~~~~

Some ``run.py`` scripts can be broken by this. Both ``set_generic``
and ``add_config`` works differently internally.

``set_generic`` and ``set_sim_option`` now only affects files added
before the call so reordering within the ``run.py`` can be needed.

``add_config`` on the test case level will no longer discard
configurations added on the test bench level. This affects users
mixing adding configurations on both test and test case level for the
same test bench. Adding a configuration on the test bench level is now
seen as a shorthand for adding the configuration to all test cases
within the test bench. Configurations are only held at the test case
level now. Before there could be configurations on multiple levels
where the most specific level ignored all others. I now recommend
writing a for loop over test_bench.get_tests() adding configurations
to each test individually, see the updated generate_tests example.

We have also forbidden to have configurations without name (""), this
is since the default configuration of all test cases has no name. The
``post_check`` and ``pre_config`` can now be set using
``set_pre_config`` also without using ``add_config`` removing the need
to add a single unnamed configuration and instead setting these in the
default configuration.

This internal restructuring has been made to allow a sane data model
of configurations where they are attached to test cases. This allows
us to expose configurations objects on the public API in the future
allowing users more control and visibility. The current behavior of
configurations is also better documented than it ever was.

I suggest reading the section on :ref:`configurations <configurations>` in the docs.

- Replace ``disable_ieee_warnings`` and ``set_pli`` with corresponding simulation options.
- Adds ``--version`` flag
- Added ``--gui`` flag for GHDL to open gtkwave. Also allows saving waveform without opening gui with ``--gtkwave-fmt`` flag.
40 changes: 20 additions & 20 deletions examples/verilog/uart/run.py
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# This Source Code Form is subject to the terms of the Mozilla Public
# License, v. 2.0. If a copy of the MPL was not distributed with this file,
# You can obtain one at http://mozilla.org/MPL/2.0/.
#
# Copyright (c) 2014-2019, Lars Asplund [email protected]

from os.path import join, dirname
from vunit.verilog import VUnit

ui = VUnit.from_argv()

src_path = join(dirname(__file__), "src")

uart_lib = ui.add_library("uart_lib")
uart_lib.add_source_files(join(src_path, "*.sv"))

tb_uart_lib = ui.add_library("tb_uart_lib")
tb_uart_lib.add_source_files(join(src_path, "test", "*.sv"))

ui.main()
# This Source Code Form is subject to the terms of the Mozilla Public
# License, v. 2.0. If a copy of the MPL was not distributed with this file,
# You can obtain one at http://mozilla.org/MPL/2.0/.
#
# Copyright (c) 2014-2019, Lars Asplund [email protected]

from os.path import join, dirname
from vunit.verilog import VUnit

ui = VUnit.from_argv()

src_path = join(dirname(__file__), "src")

uart_lib = ui.add_library("uart_lib")
uart_lib.add_source_files(join(src_path, "*.sv"))

tb_uart_lib = ui.add_library("tb_uart_lib")
tb_uart_lib.add_source_files(join(src_path, "test", "*.sv"))

ui.main()
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