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iommu: qcom: wire up fault handler
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This is quite useful for debugging.  Currently, always TERMINATE the
translation when the fault handler returns (since this is all we need
for debugging drivers).  But I expect the SVM work should eventually
let us do something more clever.

Signed-off-by: Rob Clark <[email protected]>
Signed-off-by: Alex Williamson <[email protected]>
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robclark authored and awilliam committed Nov 3, 2017
1 parent 2c40367 commit 049541e
Showing 1 changed file with 13 additions and 5 deletions.
18 changes: 13 additions & 5 deletions drivers/iommu/qcom_iommu.c
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@ struct qcom_iommu_ctx {
void __iomem *base;
bool secure_init;
u8 asid; /* asid and ctx bank # are 1:1 */
struct iommu_domain *domain;
};

struct qcom_iommu_domain {
Expand Down Expand Up @@ -194,12 +195,15 @@ static irqreturn_t qcom_iommu_fault(int irq, void *dev)
fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);

dev_err_ratelimited(ctx->dev,
"Unhandled context fault: fsr=0x%x, "
"iova=0x%016llx, fsynr=0x%x, cb=%d\n",
fsr, iova, fsynr, ctx->asid);
if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
dev_err_ratelimited(ctx->dev,
"Unhandled context fault: fsr=0x%x, "
"iova=0x%016llx, fsynr=0x%x, cb=%d\n",
fsr, iova, fsynr, ctx->asid);
}

iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
iommu_writel(ctx, ARM_SMMU_CB_RESUME, RESUME_TERMINATE);

return IRQ_HANDLED;
}
Expand Down Expand Up @@ -274,12 +278,14 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,

/* SCTLR */
reg = SCTLR_CFIE | SCTLR_CFRE | SCTLR_AFE | SCTLR_TRE |
SCTLR_M | SCTLR_S1_ASIDPNE;
SCTLR_M | SCTLR_S1_ASIDPNE | SCTLR_CFCFG;

if (IS_ENABLED(CONFIG_BIG_ENDIAN))
reg |= SCTLR_E;

iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);

ctx->domain = domain;
}

mutex_unlock(&qcom_domain->init_mutex);
Expand Down Expand Up @@ -395,6 +401,8 @@ static void qcom_iommu_detach_dev(struct iommu_domain *domain, struct device *de

/* Disable the context bank: */
iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);

ctx->domain = NULL;
}
pm_runtime_put_sync(qcom_iommu->dev);

Expand Down

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