clk: rockchip: fix incorrect parent for rk3399's {c,g}pll_aclk_perihp…

…_src There was a typo, swapping 'c' <--> 'g'. Signed-off-by: Xing Zheng <[email protected]> Signed-off-by: Brian Norris <[email protected]> Reviewed-by: Douglas Anderson <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]>
akeromi · May 30, 2016 · 3bd14ae · 3bd14ae
1 parent 176df69
commit 3bd14ae
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/drivers/clk/rockchip/clk-rk3399.c b/drivers/clk/rockchip/clk-rk3399.c
@@ -832,9 +832,9 @@ static struct rockchip_clk_branch rk3399_clk_branches[] __initdata = {
 			RK3399_CLKGATE_CON(13), 1, GFLAGS),
 
 	/* perihp */
-	GATE(0, "cpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
+	GATE(0, "cpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 0, GFLAGS),
-	GATE(0, "gpll_aclk_perihp_src", "cpll", CLK_IGNORE_UNUSED,
+	GATE(0, "gpll_aclk_perihp_src", "gpll", CLK_IGNORE_UNUSED,
 			RK3399_CLKGATE_CON(5), 1, GFLAGS),
 	COMPOSITE(ACLK_PERIHP, "aclk_perihp", mux_aclk_perihp_p, CLK_IGNORE_UNUSED,
 			RK3399_CLKSEL_CON(14), 7, 1, MFLAGS, 0, 5, DFLAGS,