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Commits on Feb 18, 2015

• [ARM] Add missing M/R class CPUs

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  4fe6d07

Commits on Feb 10, 2015

• [ARM] Add armv6s[-]m as an alias to armv6[-]m

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Commits on Feb 4, 2015

• [ARM] Fix subtarget feature set truncation when using .cpu directive

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Commits on Jan 19, 2015

• [ARM] SSAT/USAT with an 'asr llvm-mirror#32' shift should result in an undefined encoding rather than unpredictable

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  0041050

• [ARM] Fixup sign extend instruction availability w.r.t. DSP extension

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  ded2091

Commits on Dec 16, 2014

• [ARM] Prevent PerformVCVTCombine from combining a vmul/vcvt with 8 lanes

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  a9d9f7e

Commits on Oct 31, 2014

• [SCEV] Improve Scalar Evolution's use of no {un,}signed wrap flags

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  8cff277

Commits on Oct 14, 2014

• [AArch64] Fix crash with empty/pseudo-only blocks in A53 erratum (835769) workaround

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Commits on Oct 13, 2014

• [AArch64] Add workaround for Cortex-A53 erratum (835769)

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  7e67a4b

Commits on Sep 30, 2014

• Extend C disassembler API to allow specifying target features

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  95b3e16

Commits on May 23, 2014

• Fixup sys::getHostCPUFeatures crypto names so it doesn't clash with kernel headers

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  fa16c88

Commits on May 22, 2014

• Extend sys::getHostCPUFeatures to work on AArch64 platforms

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  00011c7

Commits on May 20, 2014

• [ARM64] Port basic-a64-diagnostics.s over to ARM64

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Commits on May 19, 2014

• [ARM64] Split tbz/tbnz into W/X register variant

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Commits on May 15, 2014

• [ARM64] Improve diagnostics for Cn operands in SYS instructions

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  fd76d8a

• [ARM64] Improve load/store diagnostics and forbid 32-bit register addresses

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  75aa537

• [ARM64] Parse fixed vector lanes properly so that diagnostics can be emitted

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• [ARM64] Add/Fixup diagnostics for floating point immediates

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• [ARM64] Add condition code operand type such that proper diagnostics can be emitted

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• [ARM64] Add more simple diagnostics for immediate/shift ranges

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Commits on May 12, 2014

• [ARM64] Add proper bounds checking/diagnostics to logical shifts

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  b0b5871

• [ARM64] Add diagnostics for bitfield extract/insert instructions

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  f1e0454

• [ARM64] Correct more bounds checks/diagnostics for arithmetic shift operands

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  0ce7616

• [ARM64] Move register/register MOV handling into tablegen and improve diagnostics

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  0d919c6

Commits on May 8, 2014

• [ARM64] Add diagnostics for expected arithmetic shifts

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  a37c8c0

• [ARM64] Re-work parsing of ADD/SUB shifted immediate operands

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  0d2a5d2

• [ARM64] Ensure immediates in extend operands are in a valid range

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  23f5a0b

• [ARM64] Check for proper immediate in shift/extend operands

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Commits on May 1, 2014

• [ARM64] Prefer generation of bzero on Darwin only

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• [ARM64] Conditionalize CPU specific system registers on subtarget features

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Commits on Apr 25, 2014

• [ARM64] Print preferred aliases for SFBM/UBFM in InstPrinter

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Commits on Apr 9, 2014

• [ARM64] Change SYS without a register to an alias to make disassembling more consistant.

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• [ARM64] Correctly disassemble ISB operand as ISB not DBarrier.

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• [ARM64] Properly support both apple and standard syntax for FMOV

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• [ARM64] Flag setting logical/add/sub immediate instructions don't use SP.

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