ARC: Add HS4x support

Minimal HSDK4xD support

Signed-off-by: Nikolay Agishev <[email protected]>

arch/arc/Kconfig

@@ -87,7 +87,15 @@ config CPU_HS3X
 	select CPU_HAS_DCACHE
 	select CPU_HAS_ICACHE
 	help
-	  If y, the SoC uses an ARC HS3x or HS4x CPU
+	  If y, the SoC uses an ARC HS3x CPU
+
+config CPU_HS4X
+	bool
+	select CPU_ARCHS
+	select CPU_HAS_DCACHE
+	select CPU_HAS_ICACHE
+	help
+	  If y, the SoC uses an HS4X CPU
 
 endif #ISA_ARCV2
 
@@ -278,8 +286,8 @@ config CODE_DENSITY
 	  Enable code density option to get better code density
 
 config ARC_HAS_ACCL_REGS
-	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)"
-	default y if CPU_HS3X || CPU_HS5X || CPU_HS6X
+	bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
+	default y if CPU_HS3X || CPU_HS4X || CPU_HS5X || CPU_HS6X
 	help
 	  Depending on the configuration, CPU can contain accumulator reg-pair
 	  (also referred to as r58:r59). These can also be used by gcc as GPR so
@@ -377,6 +385,13 @@ config ARC_EXCEPTION_DEBUG
 	  and parameters, at a cost of code/data size for the human-readable
 	  strings.
 
+config ARC_EARLY_SOC_INIT
+	bool "Make early stage SoC-specific initialization"
+	help
+	  Call SoC per-core setup code on early stage initialization
+	  (before C runtime initialization). Setup code is called in form of
+	  soc_early_asm_init_percpu assembler macro.
+
 endmenu
 
 config MAIN_STACK_SIZE

arch/arc/core/dsp/Kconfig

@@ -16,6 +16,12 @@ config ARC_DSP
 	help
 	  This option enables DSP and DSP instructions.
 
+config ARC_DSP_TURNED_OFF
+	bool "Turn off DSP if it presents"
+	depends on !ARC_DSP
+	help
+	  This option disables DSP block via resetting DSP_CRTL register.
+
 config ARC_DSP_SHARING
 	bool "DSP register sharing"
 	depends on ARC_DSP && MULTITHREADING

arch/arc/core/dsp/swap_dsp_macros.h

@@ -260,3 +260,10 @@ dsp_skip_load :
 #endif
 agu_skip_load :
 .endm
+
+.macro _dsp_extension_probe
+#ifdef CONFIG_ARC_DSP_TURNED_OFF
+	mov	 r0, 0 /* DSP_CTRL_DISABLED_ALL */
+	sr	 r0, [_ARC_V2_DSP_CTRL]
+#endif
+.endm

arch/arc/core/reset.S

@@ -16,6 +16,9 @@
 #include <zephyr/arch/cpu.h>
 #include <swap_macros.h>
 #include <zephyr/arch/arc/asm-compat/assembler.h>
+#ifdef CONFIG_ARC_EARLY_SOC_INIT
+  #include <soc_ctrl.h>
+#endif
 
 GDATA(z_interrupt_stacks)
 GDATA(z_main_stack)
@@ -109,6 +112,12 @@ done_icache_invalidate:
 
 done_dcache_invalidate:
 
+#ifdef CONFIG_ARC_EARLY_SOC_INIT
+	soc_early_asm_init_percpu
+#endif
+
+	_dsp_extension_probe
+
 /*
  * Init ARC internal architecture state
  * Force to initialize internal architecture state to reset values

boards/arc/hsdk4xd/CMakeLists.txt

@@ -0,0 +1,5 @@
+#
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+#
+# SPDX-License-Identifier: Apache-2.0
+#

boards/arc/hsdk4xd/Kconfig.board

@@ -0,0 +1,13 @@
+# DesignWare ARC HSDK4XD Development Kit board configuration
+
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_HSDK4XD
+	bool "ARC HSDK4XD Development Kit"
+	depends on SOC_ARC_HSDK4XD
+	help
+	  The ARC HS4x/4xD Development Kit is a ready-to-use software development
+	  platform for the ARC HS4x/4xD family of processor IP. It includes
+	  a multicore ARC HS4x/HS4xD-based chip and integrates a wide range
+	  of interfaces.

boards/arc/hsdk4xd/Kconfig.defconfig

@@ -0,0 +1,9 @@
+# Copyright (c) 2023 Synopsys, Inc. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_HSDK4XD
+
+config BOARD
+	default "hsdk4xd"
+
+endif #BOARD_HSDK4XD

boards/arc/hsdk4xd/board.cmake

@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: Apache-2.0
+board_runner_args(openocd "--use-elf")
+
+board_runner_args(mdb-hw "--jtag=digilent" "--cores=${CONFIG_MP_MAX_NUM_CPUS}")
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+include(${ZEPHYR_BASE}/boards/common/mdb-hw.board.cmake)

boards/arc/hsdk4xd/hsdk4xd.dts

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2023, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include "hsdk4xd.dtsi"
+
+/ {
+	model = "hsdk4xd";
+	compatible = "snps,hsdk4xd";
+};

boards/arc/hsdk4xd/hsdk4xd.dtsi

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2023, Synopsys, Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <synopsys/arc_hs4xd.dtsi>
+
+/ {
+
+	aliases {
+		uart-dbg = &uart_dbg;
+	};
+
+	chosen {
+		zephyr,sram = &ddr0;
+		zephyr,console = &uart_dbg;
+		zephyr,shell-uart = &uart_dbg;
+	};
+
+};
+
+arduino_spi: &spi2 {};
+
+&uart_dbg {
+	status = "okay";
+	current-speed = <115200>;
+};
+
+&creg_gpio {
+	status = "okay";
+};

boards/arc/hsdk4xd/hsdk4xd.yaml

@@ -0,0 +1,13 @@
+identifier: hsdk4xd
+name: HS4xD Development Kit
+type: mcu
+arch: arc
+toolchain:
+  - zephyr
+  - cross-compile
+  - xtools
+  - arcmwdt
+testing:
+  ignore_tags:
+    - net
+    - bluetooth

boards/arc/hsdk4xd/hsdk4xd_defconfig

@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_ARC_HSDK4XD=y
+CONFIG_BOARD_HSDK4XD=y
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
+CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_BUILD_OUTPUT_BIN=n
+CONFIG_ARCV2_INTERRUPT_UNIT=y
+CONFIG_ARCV2_TIMER=y
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_GPIO=y
+CONFIG_SMP=y
+CONFIG_MP_MAX_NUM_CPUS=4
+CONFIG_ARC_DSP_TURNED_OFF=y

boards/arc/hsdk4xd/support/openocd.cfg

@@ -0,0 +1,114 @@
+#  Copyright (C) 2019-2023 Synopsys, Inc.
+#  SPDX-License-Identifier: Apache-2.0
+#
+
+# Configure JTAG cable
+# SDP has built-in FT2232 chip, which is similar to Digilent HS-1, except that
+# it uses channel B for JTAG, instead of channel A.
+adapter driver ftdi
+
+# Only specify FTDI serial number if it is specified via
+# "set _ZEPHYR_BOARD_SERIAL 12345" before reading this script
+if { [info exists _ZEPHYR_BOARD_SERIAL] } {
+       adapter serial $_ZEPHYR_BOARD_SERIAL
+}
+
+ftdi vid_pid 0x0403 0x6010
+ftdi layout_init 0x0088 0x008b
+ftdi channel 1
+
+
+adapter speed 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS4x.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+set _TARGETNAME4 $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x100c54b1
+set _TARGETNAME3 $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x100854b1
+set _TARGETNAME2 $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x100454b1
+set _TARGETNAME1 $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x100054b1
+
+################################
+# ARC HS4x core 2
+################################
+
+target create $_TARGETNAME2 arcv2 -chain-position $_TARGETNAME2
+$_TARGETNAME2 configure -coreid $_coreid
+$_TARGETNAME2 configure -dbgbase $_dbgbase
+$_TARGETNAME2 configure -event reset-assert "arc_common_reset $_TARGETNAME2"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME2 arc cache l2 auto 1
+
+################################
+# ARC HS4x core 3
+################################
+
+target create $_TARGETNAME3 arcv2 -chain-position $_TARGETNAME3
+$_TARGETNAME3 configure -coreid $_coreid
+$_TARGETNAME3 configure -dbgbase $_dbgbase
+$_TARGETNAME3 configure -event reset-assert "arc_common_reset $_TARGETNAME3"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME3 arc cache l2 auto 1
+
+################################
+# ARC HS4x core 4
+################################
+
+target create $_TARGETNAME4 arcv2 -chain-position $_TARGETNAME4
+$_TARGETNAME4 configure -coreid $_coreid
+$_TARGETNAME4 configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME4 configure -event reset-assert "arc_hs_reset $_TARGETNAME4"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME4 arc cache l2 auto 1
+
+################################
+# ARC HS4x core 1
+################################
+
+target create $_TARGETNAME1 arcv2 -chain-position $_TARGETNAME1
+$_TARGETNAME1 configure -coreid $_coreid
+$_TARGETNAME1 configure -dbgbase $_dbgbase
+$_TARGETNAME1 configure -event reset-assert "arc_common_reset $_TARGETNAME1"
+set _coreid [expr {$_coreid + 1}]
+set _dbgbase [expr {0x00000000 | ($_coreid << 13)}]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME1 arc cache l2 auto 1
+
+target smp $_TARGETNAME1 $_TARGETNAME2 $_TARGETNAME3 $_TARGETNAME4

cmake/gcc-m-cpu.cmake

@@ -89,6 +89,8 @@ elseif("${ARCH}" STREQUAL "arc")
     set(GCC_M_CPU em4_fpuda)
   elseif(CONFIG_CPU_HS3X)
     set(GCC_M_CPU archs)
+  elseif(CONFIG_CPU_HS4X)
+    set(GCC_M_CPU hs4x)
   elseif(CONFIG_CPU_HS5X)
     set(GCC_M_CPU hs5x)
   elseif(CONFIG_CPU_HS6X)