debug: coredump: add xtensa intel adsp, support toolchains

Adds compatibility with Intel ADSP GDB from Zephyr SDK and
from Cadence toolchain to coredump_gdbserver.py.

Adds CAVS 15-25 (APL) register definitions. Implements
handle_register_single_read_packet to serve ADSP GDB
p packets.

Prevents BSA from changing between stack dump printout
and coredump by taking lock. Observed to be necessary for
accurate results on slower simulated platforms.

Signed-off-by: Lauren Murphy <[email protected]>

arch/xtensa/core/coredump.c

@@ -9,12 +9,13 @@
 #include <xtensa-asm2.h>
 
 #define ARCH_HDR_VER			1
-#define XTENSA_BLOCK_HDR_VER	1
+#define XTENSA_BLOCK_HDR_VER		2
 
 enum xtensa_soc_code {
 	XTENSA_SOC_UNKNOWN = 0,
 	XTENSA_SOC_SAMPLE_CONTROLLER,
 	XTENSA_SOC_ESP32,
+	XTENSA_SOC_INTEL_ADSP,
 };
 
 struct xtensa_arch_block {
@@ -28,14 +29,16 @@ struct xtensa_arch_block {
 	 */
 	uint8_t		soc;
 
-	/* Future versions of Xtensa coredump
-	 * may expand minimum set of registers
+	/* Future versions of Xtensa coredump may expand
+	 * minimum set of registers
 	 *
 	 * (This should stay the second field for the same
 	 * reason as the first once we have more versions)
 	 */
 	uint16_t	version;
 
+	uint8_t		toolchain;
+
 	struct {
 		/* Minimum set shown by GDB 'info registers',
 		 * skipping user-defined register EXPSTATE
@@ -101,13 +104,18 @@ void arch_coredump_info_dump(const z_arch_esf_t *esf)
 
 	arch_blk.version = XTENSA_BLOCK_HDR_VER;
 
-#if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER
-	arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER;
-#elif CONFIG_SOC_ESP32
-	arch_blk.soc = XTENSA_SOC_ESP32;
-#else
-	arch_blk.soc = XTENSA_SOC_UNKNOWN;
-#endif
+	#if CONFIG_SOC_XTENSA_SAMPLE_CONTROLLER
+		arch_blk.soc = XTENSA_SOC_SAMPLE_CONTROLLER;
+	#elif CONFIG_SOC_ESP32
+		arch_blk.soc = XTENSA_SOC_ESP32;
+	#elif CONFIG_SOC_FAMILY_INTEL_ADSP
+		arch_blk.soc = XTENSA_SOC_INTEL_ADSP;
+	#else
+		arch_blk.soc = XTENSA_SOC_UNKNOWN;
+	#endif
+
+	/* Set in top-level CMakeLists.txt for use with Xtensa coredump */
+	arch_blk.toolchain = XTENSA_TOOLCHAIN_VARIANT;
 
 	__asm__ volatile("rsr.exccause %0" : "=r"(arch_blk.r.exccause));
 

arch/xtensa/core/fatal.c

@@ -14,6 +14,7 @@
 #include <xtensa_backtrace.h>
 #endif
 #endif
+#include <zephyr/debug/coredump.h>
 #include <zephyr/logging/log.h>
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
@@ -97,7 +98,17 @@ char *z_xtensa_exccause(unsigned int cause_code)
 void z_xtensa_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
 {
 	if (esf) {
+		/* Don't want to get elbowed by xtensa_switch
+		 * in between printing registers and dumping them;
+		 * corrupts backtrace
+		 */
+		unsigned int key = arch_irq_lock();
+
 		z_xtensa_dump_stack(esf);
+
+		coredump(reason, esf, IS_ENABLED(CONFIG_MULTITHREADING) ? k_current_get() : NULL);
+
+		arch_irq_unlock(key);
 	}
 #if defined(CONFIG_XTENSA_ENABLE_BACKTRACE)
 #if XCHAL_HAVE_WINDOWED

doc/services/debugging/coredump.rst

@@ -57,6 +57,11 @@ This usually involves the following steps:
 
 4. Start the debugger corresponding to the target architecture.
 
+.. note::
+   Developers for Intel ADSP CAVS 15-25 platforms using
+   ``ZEPHYR_TOOLCHAIN_VARIANT=zephyr`` should use the debugger in the
+   ``xtensa-intel_apl_adsp`` toolchain of the SDK.
+
 Example
 -------
 

kernel/fatal.c

@@ -13,7 +13,9 @@
 #include <zephyr/logging/log_ctrl.h>
 #include <zephyr/logging/log.h>
 #include <zephyr/fatal.h>
+#ifndef	CONFIG_XTENSA
 #include <zephyr/debug/coredump.h>
+#endif
 
 LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);
 
@@ -122,7 +124,9 @@ void z_fatal_error(unsigned int reason, const z_arch_esf_t *esf)
 	LOG_ERR("Current thread: %p (%s)", thread,
 		thread_name_get(thread));
 
+#ifndef CONFIG_XTENSA
 	coredump(reason, esf, thread);
+#endif
 
 	k_sys_fatal_error_handler(reason, esf);