Skip to content

Commit

Permalink
Add a -stress-regalloc=<N> option.
Browse files Browse the repository at this point in the history
This will limit all register classes to N registers in order to stress
test register allocation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151379 91177308-0d34-0410-b5e6-96231b3b80d8
  • Loading branch information
stoklund committed Feb 24, 2012
1 parent 3161039 commit 27bc818
Showing 1 changed file with 9 additions and 1 deletion.
10 changes: 9 additions & 1 deletion lib/CodeGen/RegisterClassInfo.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -18,12 +18,16 @@
#include "RegisterClassInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"

#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/raw_ostream.h"

using namespace llvm;

cl::opt<unsigned> StressRA("stress-regalloc", cl::Hidden, cl::init(0),
cl::value_desc("N"),
cl::desc("Limit all regclasses to N registers"));

RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0)
{}

Expand Down Expand Up @@ -99,6 +103,10 @@ void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
// CSR aliases go after the volatile registers, preserve the target's order.
std::copy(CSRAlias.begin(), CSRAlias.end(), &RCI.Order[N]);

// Register allocator stress test. Clip register class to N registers.
if (StressRA && RCI.NumRegs > StressRA)
RCI.NumRegs = StressRA;

// Check if RC is a proper sub-class.
if (const TargetRegisterClass *Super = TRI->getLargestLegalSuperClass(RC))
if (Super != RC && getNumAllocatableRegs(Super) > RCI.NumRegs)
Expand Down

0 comments on commit 27bc818

Please sign in to comment.