Skip to content

Pull requests: amaranth-lang/amaranth-soc

New pull request New
10 Open 61 Closed
10 Open 61 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Milestones
Filter by milestone
Loading
Reviews
Filter by reviews
No reviews Review required Approved review Changes requested
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Pull requests list

[WIP] Add reference-level documentation
#82 opened Apr 9, 2024 by jfng • Draft
1
Implement RFC 60: UART peripheral.
#81 opened Mar 29, 2024 by jfng • Draft
1 of 2 tasks
1
Add annotations for memory maps, wishbone and CSR primitives.
#58 opened Dec 5, 2023 by jfng
7
wishbone.bus.Decoder: Only assert stb when slave is selected
#31 opened Aug 23, 2021 by antonblanchard
2
csr/bus: Take data width into account for register writes
#30 opened May 14, 2021 by kbeckmann
SRAM bus
#29 opened Apr 20, 2021 by Fatsie
CSR: Export Wishbone bridge from nmigen_soc.csr
#28 opened Apr 20, 2021 by Fatsie
Make optional properties return None while uninitialized.
#26 opened Aug 22, 2020 by jfng
1
[WIP]wishbone.Connector class
#21 opened Jul 1, 2020 by Fatsie • Changes requested
35
csr.periph: add Peripheral base class.
#11 opened Mar 23, 2020 by jfng
5
ProTip! Follow long discussions with comments:>50.