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Commits on Sep 4, 2022

• docs/system: openrisc: Add OpenRISC documentation

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• target/openrisc: Interrupt handling fixes

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• target/openrisc: Enable MTTCG

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• target/openrisc: Add interrupted CPU to log

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• hw/openrisc: Initialize timer time at startup

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• hw/openrisc: Add PCI bus support to virt

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• hw/openrisc: Add the OpenRISC virtual machine

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• goldfish_rtc: Add big-endian property

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• target/openrisc: Fix memory reading in debugger

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• hw/openrisc: Split re-usable boot time apis out to boot.c

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Commits on May 15, 2022

• target/openrisc: Do not reset delay slot flag on early tb exit

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Commits on Feb 26, 2022

• hw/openrisc/openrisc_sim: Add support for initrd loading

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• hw/openrisc/openrisc_sim: Add automatic device tree generation

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Commits on Feb 25, 2022

• hw/openrisc/openrisc_sim: Increase max_cpus to 4

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• hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART

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• hw/openrisc/openrisc_sim: Parameterize initialization

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• hw/openrisc/openrisc_sim: Create machine state for or1ksim

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Commits on Jan 17, 2020

• target/openrisc: Fix FPCSR mask to allow setting DZF

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Commits on Jul 3, 2018

• target/openrisc: Fix writes to interrupt mask register

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• target/openrisc: Fix delay slot exception flag to match spec

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Commits on Oct 20, 2017

• openrisc: Only kick cpu on timeout, not on update

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• openrisc: Initial SMP support

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• openrisc/cputimer: Perparation for Multicore

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• target/openrisc: Make coreid and numcores variable

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• openrisc/ompic: Add OpenRISC Multicore PIC (OMPIC)

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Commits on May 4, 2017

• target/openrisc: Support non-busy idle state using PMR SPR

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• target/openrisc: Remove duplicate features property

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• target/openrisc: Implement full vmstate serialization

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• migration: Add VMSTATE_STRUCT_2DARRAY()

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• target/openrisc: implement shadow registers

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• migration: Add VMSTATE_UINTTL_2DARRAY()

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• target/openrisc: add numcores and coreid support

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• target/openrisc: Fixes for memory debugging

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Commits on Apr 21, 2017

• MAINTAINERS: Add myself as openrisc maintainer

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Commits on Feb 13, 2017

• target/openrisc: Fix exception handling status registers

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