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Merge tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/dr…
…m/drm Pull drm updates from Dave Airlie: "This starts to support NVIDIA volta hardware with nouveau, and adds amdgpu support for the GPU in the Kabylake-G (the intel + radeon single package chip), along with some initial Intel icelake enabling. Summary: New Drivers: - v3d - driver for broadcom V3D V3.x+ hardware - xen-front - XEN PV display frontend core: - handle zpos normalization in the core - stop looking at legacy pointers in atomic paths - improved scheduler documentation - improved aspect ratio validation - aspect ratio support for 64:27 and 256:135 - drop unused control node code. i915: - Icelake (ICL) enabling - GuC/HuC refactoring - PSR/PSR2 enabling and fixes - DPLL management refactoring - DP MST fixes - NV12 enabling - HDCP improvements - GEM/Execlist/reset improvements - GVT improvements - stolen memory first 4k fix amdgpu: - Vega 20 support - VEGAM support (Kabylake-G) - preOS scanout buffer reservation - power management gfxoff support for raven - SR-IOV fixes - Vega10 power profiles and clock voltage control - scatter/gather display support on CZ/ST amdkfd: - GFX9 dGPU support - userptr memory mapping nouveau: - major refactoring for Volta GV100 support tda998x: - HDMI i2c CEC support etnaviv: - removed unused logging code - license text cleanups - MMU handling improvements - timeout fence fix for 50 days uptime tegra: - IOMMU support in gr2d/gr3d drivers - zpos support vc4: - syncobj support - CTM, plane alpha and async cursor support analogix_dp: - HPD and aux chan fixes sun4i: - MIPI DSI support tilcdc: - clock divider fixes for OMAP-l138 LCDK board rcar-du: - R8A77965 support - dma-buf fences fixes - hardware indexed crtc/du group handling - generic zplane property support atmel-hclcdc: - generic zplane property support mediatek: - use generic video mode function exynos: - S5PV210 FIMD variant support - IPP v2 framework - more HW overlays support" * tag 'drm-next-2018-06-06-1' of git://anongit.freedesktop.org/drm/drm: (1286 commits) drm/amdgpu: fix 32-bit build warning drm/exynos: fimc: signedness bug in fimc_setup_clocks() drm/exynos: scaler: fix static checker warning drm/amdgpu: Use dev_info() to report amdkfd is not supported for this ASIC drm/amd/display: Remove use of division operator for long longs drm/amdgpu: Update GFX info structure to match what vega20 used drm/amdgpu/pp: remove duplicate assignment drm/sched: add rcu_barrier after entity fini drm/amdgpu: move VM BOs on LRU again drm/amdgpu: consistenly use VM moved flag drm/amdgpu: kmap PDs/PTs in amdgpu_vm_update_directories drm/amdgpu: further optimize amdgpu_vm_handle_moved drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2 drm/amdgpu: rework VM state machine lock handling v2 drm/amdgpu: Add runtime VCN PG support drm/amdgpu: Enable VCN static PG by default on RV drm/amdgpu: Add VCN static PG support on RV drm/amdgpu: Enable VCN CG by default on RV drm/amdgpu: Add static CG control for VCN on RV drm/exynos: Fix default value for zpos plane property ...
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133
Documentation/devicetree/bindings/display/bridge/cdns,dsi.txt
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| Cadence DSI bridge | ||
| ================== | ||
|
|
||
| The Cadence DSI bridge is a DPI to DSI bridge supporting up to 4 DSI lanes. | ||
|
|
||
| Required properties: | ||
| - compatible: should be set to "cdns,dsi". | ||
| - reg: physical base address and length of the controller's registers. | ||
| - interrupts: interrupt line connected to the DSI bridge. | ||
| - clocks: DSI bridge clocks. | ||
| - clock-names: must contain "dsi_p_clk" and "dsi_sys_clk". | ||
| - phys: phandle link to the MIPI D-PHY controller. | ||
| - phy-names: must contain "dphy". | ||
| - #address-cells: must be set to 1. | ||
| - #size-cells: must be set to 0. | ||
|
|
||
| Optional properties: | ||
| - resets: DSI reset lines. | ||
| - reset-names: can contain "dsi_p_rst". | ||
|
|
||
| Required subnodes: | ||
| - ports: Ports as described in Documentation/devicetree/bindings/graph.txt. | ||
| 2 ports are available: | ||
| * port 0: this port is only needed if some of your DSI devices are | ||
| controlled through an external bus like I2C or SPI. Can have at | ||
| most 4 endpoints. The endpoint number is directly encoding the | ||
| DSI virtual channel used by this device. | ||
| * port 1: represents the DPI input. | ||
| Other ports will be added later to support the new kind of inputs. | ||
|
|
||
| - one subnode per DSI device connected on the DSI bus. Each DSI device should | ||
| contain a reg property encoding its virtual channel. | ||
|
|
||
| Cadence DPHY | ||
| ============ | ||
|
|
||
| Cadence DPHY block. | ||
|
|
||
| Required properties: | ||
| - compatible: should be set to "cdns,dphy". | ||
| - reg: physical base address and length of the DPHY registers. | ||
| - clocks: DPHY reference clocks. | ||
| - clock-names: must contain "psm" and "pll_ref". | ||
| - #phy-cells: must be set to 0. | ||
|
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||
|
|
||
| Example: | ||
| dphy0: dphy@fd0e0000{ | ||
| compatible = "cdns,dphy"; | ||
| reg = <0x0 0xfd0e0000 0x0 0x1000>; | ||
| clocks = <&psm_clk>, <&pll_ref_clk>; | ||
| clock-names = "psm", "pll_ref"; | ||
| #phy-cells = <0>; | ||
| }; | ||
|
|
||
| dsi0: dsi@fd0c0000 { | ||
| compatible = "cdns,dsi"; | ||
| reg = <0x0 0xfd0c0000 0x0 0x1000>; | ||
| clocks = <&pclk>, <&sysclk>; | ||
| clock-names = "dsi_p_clk", "dsi_sys_clk"; | ||
| interrupts = <1>; | ||
| phys = <&dphy0>; | ||
| phy-names = "dphy"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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||
| port@1 { | ||
| reg = <1>; | ||
| dsi0_dpi_input: endpoint { | ||
| remote-endpoint = <&xxx_dpi_output>; | ||
| }; | ||
| }; | ||
| }; | ||
|
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||
| panel: dsi-dev@0 { | ||
| compatible = "<vendor,panel>"; | ||
| reg = <0>; | ||
| }; | ||
| }; | ||
|
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||
| or | ||
|
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| dsi0: dsi@fd0c0000 { | ||
| compatible = "cdns,dsi"; | ||
| reg = <0x0 0xfd0c0000 0x0 0x1000>; | ||
| clocks = <&pclk>, <&sysclk>; | ||
| clock-names = "dsi_p_clk", "dsi_sys_clk"; | ||
| interrupts = <1>; | ||
| phys = <&dphy1>; | ||
| phy-names = "dphy"; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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||
| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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| port@0 { | ||
| reg = <0>; | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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| dsi0_output: endpoint@0 { | ||
| reg = <0>; | ||
| remote-endpoint = <&dsi_panel_input>; | ||
| }; | ||
| }; | ||
|
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| port@1 { | ||
| reg = <1>; | ||
| dsi0_dpi_input: endpoint { | ||
| remote-endpoint = <&xxx_dpi_output>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; | ||
|
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||
| i2c@xxx { | ||
| panel: panel@59 { | ||
| compatible = "<vendor,panel>"; | ||
| reg = <0x59>; | ||
|
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||
| port { | ||
| dsi_panel_input: endpoint { | ||
| remote-endpoint = <&dsi0_output>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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60
Documentation/devicetree/bindings/display/bridge/thine,thc63lvd1024.txt
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| Thine Electronics THC63LVD1024 LVDS decoder | ||
| ------------------------------------------- | ||
|
|
||
| The THC63LVD1024 is a dual link LVDS receiver designed to convert LVDS streams | ||
| to parallel data outputs. The chip supports single/dual input/output modes, | ||
| handling up to two LVDS input streams and up to two digital CMOS/TTL outputs. | ||
|
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| Single or dual operation mode, output data mapping and DDR output modes are | ||
| configured through input signals and the chip does not expose any control bus. | ||
|
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| Required properties: | ||
| - compatible: Shall be "thine,thc63lvd1024" | ||
| - vcc-supply: Power supply for TTL output, TTL CLOCKOUT signal, LVDS input, | ||
| PPL and digital circuitry | ||
|
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||
| Optional properties: | ||
| - powerdown-gpios: Power down GPIO signal, pin name "/PDWN". Active low | ||
| - oe-gpios: Output enable GPIO signal, pin name "OE". Active high | ||
|
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| The THC63LVD1024 video port connections are modeled according | ||
| to OF graph bindings specified by Documentation/devicetree/bindings/graph.txt | ||
|
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| Required video port nodes: | ||
| - port@0: First LVDS input port | ||
| - port@2: First digital CMOS/TTL parallel output | ||
|
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||
| Optional video port nodes: | ||
| - port@1: Second LVDS input port | ||
| - port@3: Second digital CMOS/TTL parallel output | ||
|
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||
| Example: | ||
| -------- | ||
|
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| thc63lvd1024: lvds-decoder { | ||
| compatible = "thine,thc63lvd1024"; | ||
|
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| vcc-supply = <®_lvds_vcc>; | ||
| powerdown-gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; | ||
|
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| ports { | ||
| #address-cells = <1>; | ||
| #size-cells = <0>; | ||
|
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| port@0 { | ||
| reg = <0>; | ||
|
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| lvds_dec_in_0: endpoint { | ||
| remote-endpoint = <&lvds_out>; | ||
| }; | ||
| }; | ||
|
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| port@2{ | ||
| reg = <2>; | ||
|
|
||
| lvds_dec_out_2: endpoint { | ||
| remote-endpoint = <&adv7511_in>; | ||
| }; | ||
| }; | ||
| }; | ||
| }; |
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