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arm64: dts: qcom: timer should use only 32-bit size
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There's no reason the timer needs > 32-bits of address or size.
Since we using 32-bit size, we need to define ranges properly.

Fixes warnings as:
```
arch/arm64/boot/dts/qcom/sdm845-oneplus-fajita.dt.yaml: timer@17c90000: #size-cells:0:0: 1 was expected
        From schema: Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
```

Signed-off-by: David Heidelberg <[email protected]>
Signed-off-by: Bjorn Andersson <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
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@okias @andersson
okias authored and andersson committed Jun 27, 2022
1 parent 0e3e654 commit 458ebdb
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Showing 9 changed files with 99 additions and 99 deletions.
22 changes: 11 additions & 11 deletions arch/arm64/boot/dts/qcom/ipq6018.dtsi
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Expand Up @@ -525,59 +525,59 @@
};

timer@b120000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x10000000>;
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x0b120000 0x0 0x1000>;

frame@b120000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b121000 0x0 0x1000>,
<0x0 0x0b122000 0x0 0x1000>;
reg = <0x0b121000 0x1000>,
<0x0b122000 0x1000>;
};

frame@b123000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0xb123000 0x0 0x1000>;
reg = <0x0b123000 0x1000>;
status = "disabled";
};

frame@b124000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b124000 0x0 0x1000>;
reg = <0x0b124000 0x1000>;
status = "disabled";
};

frame@b125000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b125000 0x0 0x1000>;
reg = <0x0b125000 0x1000>;
status = "disabled";
};

frame@b126000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b126000 0x0 0x1000>;
reg = <0x0b126000 0x1000>;
status = "disabled";
};

frame@b127000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b127000 0x0 0x1000>;
reg = <0x0b127000 0x1000>;
status = "disabled";
};

frame@b128000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x0b128000 0x0 0x1000>;
reg = <0x0b128000 0x1000>;
status = "disabled";
};
};
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22 changes: 11 additions & 11 deletions arch/arm64/boot/dts/qcom/sc7180.dtsi
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Expand Up @@ -3379,59 +3379,59 @@
};

timer@17c20000{
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;

frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c21000 0 0x1000>,
<0 0x17c22000 0 0x1000>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};

frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c23000 0 0x1000>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};

frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c25000 0 0x1000>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};

frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c27000 0 0x1000>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};

frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c29000 0 0x1000>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};

frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2b000 0 0x1000>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};

frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2d000 0 0x1000>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
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22 changes: 11 additions & 11 deletions arch/arm64/boot/dts/qcom/sc7280.dtsi
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Expand Up @@ -4898,59 +4898,59 @@
};

timer@17c20000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c20000 0 0x1000>;

frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c21000 0 0x1000>,
<0 0x17c22000 0 0x1000>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};

frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c23000 0 0x1000>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};

frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c25000 0 0x1000>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};

frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c27000 0 0x1000>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};

frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c29000 0 0x1000>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};

frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2b000 0 0x1000>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};

frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17c2d000 0 0x1000>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
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22 changes: 11 additions & 11 deletions arch/arm64/boot/dts/qcom/sdm845.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -4943,59 +4943,59 @@
};

timer@17c90000 {
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;
compatible = "arm,armv7-timer-mem";
reg = <0 0x17c90000 0 0x1000>;

frame@17ca0000 {
frame-number = <0>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17ca0000 0 0x1000>,
<0 0x17cb0000 0 0x1000>;
reg = <0x17ca0000 0x1000>,
<0x17cb0000 0x1000>;
};

frame@17cc0000 {
frame-number = <1>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17cc0000 0 0x1000>;
reg = <0x17cc0000 0x1000>;
status = "disabled";
};

frame@17cd0000 {
frame-number = <2>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17cd0000 0 0x1000>;
reg = <0x17cd0000 0x1000>;
status = "disabled";
};

frame@17ce0000 {
frame-number = <3>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17ce0000 0 0x1000>;
reg = <0x17ce0000 0x1000>;
status = "disabled";
};

frame@17cf0000 {
frame-number = <4>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17cf0000 0 0x1000>;
reg = <0x17cf0000 0x1000>;
status = "disabled";
};

frame@17d00000 {
frame-number = <5>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17d00000 0 0x1000>;
reg = <0x17d00000 0x1000>;
status = "disabled";
};

frame@17d10000 {
frame-number = <6>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0 0x17d10000 0 0x1000>;
reg = <0x17d10000 0x1000>;
status = "disabled";
};
};
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22 changes: 11 additions & 11 deletions arch/arm64/boot/dts/qcom/sm6350.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -1304,57 +1304,57 @@
compatible = "arm,armv7-timer-mem";
reg = <0x0 0x17c20000 0x0 0x1000>;
clock-frequency = <19200000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0x20000000>;

frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c21000 0x0 0x1000>,
<0x0 0x17c22000 0x0 0x1000>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};

frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c23000 0x0 0x1000>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};

frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c25000 0x0 0x1000>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};

frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c27000 0x0 0x1000>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};

frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c29000 0x0 0x1000>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};

frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2b000 0x0 0x1000>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};

frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x0 0x17c2d000 0x0 0x1000>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
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