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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (37 commits) smc91c92_cs: fix the problem of "Unable to find hardware address" r8169: clean up my printk uglyness net: Hook up cxgb4 to Kconfig and Makefile cxgb4: Add main driver file and driver Makefile cxgb4: Add remaining driver headers and L2T management cxgb4: Add packet queues and packet DMA code cxgb4: Add HW and FW support code cxgb4: Add register, message, and FW definitions netlabel: Fix several rcu_dereference() calls used without RCU read locks bonding: fix potential deadlock in bond_uninit() net: check the length of the socket address passed to connect(2) stmmac: add documentation for the driver. stmmac: fix kconfig for crc32 build error be2net: fix bug in vlan rx path for big endian architecture be2net: fix flashing on big endian architectures be2net: fix a bug in flashing the redboot section bonding: bond_xmit_roundrobin() fix drivers/net: Add missing unlock net: gianfar - align BD ring size console messages net: gianfar - initialize per-queue statistics ...
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STMicroelectronics 10/100/1000 Synopsys Ethernet driver | ||
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Copyright (C) 2007-2010 STMicroelectronics Ltd | ||
Author: Giuseppe Cavallaro <[email protected]> | ||
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This is the driver for the MAC 10/100/1000 on-chip Ethernet controllers | ||
(Synopsys IP blocks); it has been fully tested on STLinux platforms. | ||
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Currently this network device driver is for all STM embedded MAC/GMAC | ||
(7xxx SoCs). | ||
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DWC Ether MAC 10/100/1000 Universal version 3.41a and DWC Ether MAC 10/100 | ||
Universal version 4.0 have been used for developing the first code | ||
implementation. | ||
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Please, for more information also visit: www.stlinux.com | ||
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1) Kernel Configuration | ||
The kernel configuration option is STMMAC_ETH: | ||
Device Drivers ---> Network device support ---> Ethernet (1000 Mbit) ---> | ||
STMicroelectronics 10/100/1000 Ethernet driver (STMMAC_ETH) | ||
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2) Driver parameters list: | ||
debug: message level (0: no output, 16: all); | ||
phyaddr: to manually provide the physical address to the PHY device; | ||
dma_rxsize: DMA rx ring size; | ||
dma_txsize: DMA tx ring size; | ||
buf_sz: DMA buffer size; | ||
tc: control the HW FIFO threshold; | ||
tx_coe: Enable/Disable Tx Checksum Offload engine; | ||
watchdog: transmit timeout (in milliseconds); | ||
flow_ctrl: Flow control ability [on/off]; | ||
pause: Flow Control Pause Time; | ||
tmrate: timer period (only if timer optimisation is configured). | ||
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3) Command line options | ||
Driver parameters can be also passed in command line by using: | ||
stmmaceth=dma_rxsize:128,dma_txsize:512 | ||
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4) Driver information and notes | ||
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4.1) Transmit process | ||
The xmit method is invoked when the kernel needs to transmit a packet; it sets | ||
the descriptors in the ring and informs the DMA engine that there is a packet | ||
ready to be transmitted. | ||
Once the controller has finished transmitting the packet, an interrupt is | ||
triggered; So the driver will be able to release the socket buffers. | ||
By default, the driver sets the NETIF_F_SG bit in the features field of the | ||
net_device structure enabling the scatter/gather feature. | ||
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4.2) Receive process | ||
When one or more packets are received, an interrupt happens. The interrupts | ||
are not queued so the driver has to scan all the descriptors in the ring during | ||
the receive process. | ||
This is based on NAPI so the interrupt handler signals only if there is work to be | ||
done, and it exits. | ||
Then the poll method will be scheduled at some future point. | ||
The incoming packets are stored, by the DMA, in a list of pre-allocated socket | ||
buffers in order to avoid the memcpy (Zero-copy). | ||
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4.3) Timer-Driver Interrupt | ||
Instead of having the device that asynchronously notifies the frame receptions, the | ||
driver configures a timer to generate an interrupt at regular intervals. | ||
Based on the granularity of the timer, the frames that are received by the device | ||
will experience different levels of latency. Some NICs have dedicated timer | ||
device to perform this task. STMMAC can use either the RTC device or the TMU | ||
channel 2 on STLinux platforms. | ||
The timers frequency can be passed to the driver as parameter; when change it, | ||
take care of both hardware capability and network stability/performance impact. | ||
Several performance tests on STM platforms showed this optimisation allows to spare | ||
the CPU while having the maximum throughput. | ||
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4.4) WOL | ||
Wake up on Lan feature through Magic Frame is only supported for the GMAC | ||
core. | ||
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4.5) DMA descriptors | ||
Driver handles both normal and enhanced descriptors. The latter has been only | ||
tested on DWC Ether MAC 10/100/1000 Universal version 3.41a. | ||
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4.6) Ethtool support | ||
Ethtool is supported. Driver statistics and internal errors can be taken using: | ||
ethtool -S ethX command. It is possible to dump registers etc. | ||
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4.7) Jumbo and Segmentation Offloading | ||
Jumbo frames are supported and tested for the GMAC. | ||
The GSO has been also added but it's performed in software. | ||
LRO is not supported. | ||
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4.8) Physical | ||
The driver is compatible with PAL to work with PHY and GPHY devices. | ||
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4.9) Platform information | ||
Several information came from the platform; please refer to the | ||
driver's Header file in include/linux directory. | ||
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struct plat_stmmacenet_data { | ||
int bus_id; | ||
int pbl; | ||
int has_gmac; | ||
void (*fix_mac_speed)(void *priv, unsigned int speed); | ||
void (*bus_setup)(unsigned long ioaddr); | ||
#ifdef CONFIG_STM_DRIVERS | ||
struct stm_pad_config *pad_config; | ||
#endif | ||
void *bsp_priv; | ||
}; | ||
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Where: | ||
- pbl (Programmable Burst Length) is maximum number of | ||
beats to be transferred in one DMA transaction. | ||
GMAC also enables the 4xPBL by default. | ||
- fix_mac_speed and bus_setup are used to configure internal target | ||
registers (on STM platforms); | ||
- has_gmac: GMAC core is on board (get it at run-time in the next step); | ||
- bus_id: bus identifier. | ||
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struct plat_stmmacphy_data { | ||
int bus_id; | ||
int phy_addr; | ||
unsigned int phy_mask; | ||
int interface; | ||
int (*phy_reset)(void *priv); | ||
void *priv; | ||
}; | ||
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Where: | ||
- bus_id: bus identifier; | ||
- phy_addr: physical address used for the attached phy device; | ||
set it to -1 to get it at run-time; | ||
- interface: physical MII interface mode; | ||
- phy_reset: hook to reset HW function. | ||
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TODO: | ||
- Continue to make the driver more generic and suitable for other Synopsys | ||
Ethernet controllers used on other architectures (i.e. ARM). | ||
- 10G controllers are not supported. | ||
- MAC uses Normal descriptors and GMAC uses enhanced ones. | ||
This is a limit that should be reviewed. MAC could want to | ||
use the enhanced structure. | ||
- Checksumming: Rx/Tx csum is done in HW in case of GMAC only. | ||
- Review the timer optimisation code to use an embedded device that seems to be | ||
available in new chip generations. |
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@@ -2582,6 +2582,31 @@ config CHELSIO_T3 | |
To compile this driver as a module, choose M here: the module | ||
will be called cxgb3. | ||
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config CHELSIO_T4_DEPENDS | ||
tristate | ||
depends on PCI && INET | ||
default y | ||
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config CHELSIO_T4 | ||
tristate "Chelsio Communications T4 Ethernet support" | ||
depends on CHELSIO_T4_DEPENDS | ||
select FW_LOADER | ||
select MDIO | ||
help | ||
This driver supports Chelsio T4-based gigabit and 10Gb Ethernet | ||
adapters. | ||
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For general information about Chelsio and our products, visit | ||
our website at <http://www.chelsio.com>. | ||
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For customer support, please visit our customer support page at | ||
<http://www.chelsio.com/support.htm>. | ||
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Please send feedback to <[email protected]>. | ||
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To compile this driver as a module choose M here; the module | ||
will be called cxgb4. | ||
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config EHEA | ||
tristate "eHEA Ethernet support" | ||
depends on IBMEBUS && INET && SPARSEMEM | ||
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# | ||
# Chelsio T4 driver | ||
# | ||
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obj-$(CONFIG_CHELSIO_T4) += cxgb4.o | ||
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cxgb4-objs := cxgb4_main.o l2t.o t4_hw.o sge.o |
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