Skip to content

Commit

Permalink
clk: qcom: clk-alpha-pll: add support for zonda pll
Browse files Browse the repository at this point in the history
Ported over from the downstream driver. Will be used by SM8250 CAMCC.

Signed-off-by: Jonathan Marek <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Stephen Boyd <[email protected]>
  • Loading branch information
flto authored and bebarino committed Jun 28, 2021
1 parent 652c96b commit f21b6bf
Show file tree
Hide file tree
Showing 2 changed files with 180 additions and 0 deletions.
174 changes: 174 additions & 0 deletions drivers/clk/qcom/clk-alpha-pll.c
Original file line number Diff line number Diff line change
Expand Up @@ -126,6 +126,19 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
[PLL_OFF_TEST_CTL_U] = 0x1c,
[PLL_OFF_STATUS] = 0x2c,
},
[CLK_ALPHA_PLL_TYPE_ZONDA] = {
[PLL_OFF_L_VAL] = 0x04,
[PLL_OFF_ALPHA_VAL] = 0x08,
[PLL_OFF_USER_CTL] = 0x0c,
[PLL_OFF_CONFIG_CTL] = 0x10,
[PLL_OFF_CONFIG_CTL_U] = 0x14,
[PLL_OFF_CONFIG_CTL_U1] = 0x18,
[PLL_OFF_TEST_CTL] = 0x1c,
[PLL_OFF_TEST_CTL_U] = 0x20,
[PLL_OFF_TEST_CTL_U1] = 0x24,
[PLL_OFF_OPMODE] = 0x28,
[PLL_OFF_STATUS] = 0x38,
},
};
EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);

Expand Down Expand Up @@ -162,6 +175,11 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
#define LUCID_5LPE_PLL_LATCH_INPUT BIT(14)
#define LUCID_5LPE_ENABLE_VOTE_RUN BIT(21)

/* ZONDA PLL specific */
#define ZONDA_PLL_OUT_MASK 0xf
#define ZONDA_STAY_IN_CFA BIT(16)
#define ZONDA_PLL_FREQ_LOCK_DET BIT(29)

#define pll_alpha_width(p) \
((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \
ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)
Expand Down Expand Up @@ -208,6 +226,9 @@ static int wait_for_pll(struct clk_alpha_pll *pll, u32 mask, bool inverse,
#define wait_for_pll_enable_lock(pll) \
wait_for_pll(pll, PLL_LOCK_DET, 0, "enable")

#define wait_for_zonda_pll_freq_lock(pll) \
wait_for_pll(pll, ZONDA_PLL_FREQ_LOCK_DET, 0, "freq enable")

#define wait_for_pll_disable(pll) \
wait_for_pll(pll, PLL_ACTIVE_FLAG, 1, "disable")

Expand Down Expand Up @@ -1777,3 +1798,156 @@ const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops = {
.set_rate = clk_lucid_5lpe_pll_postdiv_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_postdiv_lucid_5lpe_ops);

void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config)
{
clk_alpha_pll_write_config(regmap, PLL_L_VAL(pll), config->l);
clk_alpha_pll_write_config(regmap, PLL_ALPHA_VAL(pll), config->alpha);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL(pll), config->config_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U(pll), config->config_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_CONFIG_CTL_U1(pll), config->config_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL(pll), config->user_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U(pll), config->user_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_USER_CTL_U1(pll), config->user_ctl_hi1_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL(pll), config->test_ctl_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U(pll), config->test_ctl_hi_val);
clk_alpha_pll_write_config(regmap, PLL_TEST_CTL_U1(pll), config->test_ctl_hi1_val);

regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, 0);

/* Disable PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);

/* Set operation mode to OFF */
regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);

/* Place the PLL in STANDBY mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
}
EXPORT_SYMBOL_GPL(clk_zonda_pll_configure);

static int clk_zonda_pll_enable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;
int ret;

regmap_read(regmap, PLL_MODE(pll), &val);

/* If in FSM mode, just vote for it */
if (val & PLL_VOTE_FSM_ENA) {
ret = clk_enable_regmap(hw);
if (ret)
return ret;
return wait_for_pll_enable_active(pll);
}

/* Get the PLL out of bypass mode */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_BYPASSNL, PLL_BYPASSNL);

/*
* H/W requires a 1us delay between disabling the bypass and
* de-asserting the reset.
*/
udelay(1);

regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);

/* Set operation mode to RUN */
regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);

regmap_read(regmap, PLL_TEST_CTL(pll), &val);

/* If cfa mode then poll for freq lock */
if (val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;

/* Enable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, ZONDA_PLL_OUT_MASK);

/* Enable the global PLL outputs */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, PLL_OUTCTRL);

return 0;
}

static void clk_zonda_pll_disable(struct clk_hw *hw)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
struct regmap *regmap = pll->clkr.regmap;
u32 val;

regmap_read(regmap, PLL_MODE(pll), &val);

/* If in FSM mode, just unvote it */
if (val & PLL_VOTE_FSM_ENA) {
clk_disable_regmap(hw);
return;
}

/* Disable the global PLL output */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);

/* Disable the PLL outputs */
regmap_update_bits(regmap, PLL_USER_CTL(pll), ZONDA_PLL_OUT_MASK, 0);

/* Put the PLL in bypass and reset */
regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N | PLL_BYPASSNL, 0);

/* Place the PLL mode in OFF state */
regmap_write(regmap, PLL_OPMODE(pll), 0x0);
}

static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long prate)
{
struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
unsigned long rrate;
u32 test_ctl_val;
u32 l, alpha_width = pll_alpha_width(pll);
u64 a;
int ret;

rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);

ret = alpha_pll_check_rate_margin(hw, rrate, rate);
if (ret < 0)
return ret;

regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);

/* Wait before polling for the frequency latch */
udelay(5);

/* Read stay in cfa mode */
regmap_read(pll->clkr.regmap, PLL_TEST_CTL(pll), &test_ctl_val);

/* If cfa mode then poll for freq lock */
if (test_ctl_val & ZONDA_STAY_IN_CFA)
ret = wait_for_zonda_pll_freq_lock(pll);
else
ret = wait_for_pll_enable_lock(pll);
if (ret)
return ret;

/* Wait for PLL output to stabilize */
udelay(100);
return 0;
}

const struct clk_ops clk_alpha_pll_zonda_ops = {
.enable = clk_zonda_pll_enable,
.disable = clk_zonda_pll_disable,
.is_enabled = clk_trion_pll_is_enabled,
.recalc_rate = clk_trion_pll_recalc_rate,
.round_rate = clk_alpha_pll_round_rate,
.set_rate = clk_zonda_pll_set_rate,
};
EXPORT_SYMBOL(clk_alpha_pll_zonda_ops);
6 changes: 6 additions & 0 deletions drivers/clk/qcom/clk-alpha-pll.h
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ enum {
CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_LUCID = CLK_ALPHA_PLL_TYPE_TRION,
CLK_ALPHA_PLL_TYPE_AGERA,
CLK_ALPHA_PLL_TYPE_ZONDA,
CLK_ALPHA_PLL_TYPE_MAX,
};

Expand Down Expand Up @@ -148,6 +149,9 @@ extern const struct clk_ops clk_alpha_pll_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_fixed_lucid_5lpe_ops;
extern const struct clk_ops clk_alpha_pll_postdiv_lucid_5lpe_ops;

extern const struct clk_ops clk_alpha_pll_zonda_ops;
#define clk_alpha_pll_postdiv_zonda_ops clk_alpha_pll_postdiv_fabia_ops

void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);
void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
Expand All @@ -159,6 +163,8 @@ void clk_agera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
#define clk_lucid_pll_configure(pll, regmap, config) \
clk_trion_pll_configure(pll, regmap, config)

void clk_zonda_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
const struct alpha_pll_config *config);


#endif

0 comments on commit f21b6bf

Please sign in to comment.