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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/gi…
…t/arm/arm-soc
Pull ARM DT updates from Arnd Bergmann:
"These are all the updates to device tree files for 32-bit platforms,
which as usual makes up the bulk of the ARM SoC changes: 462 non-merge
changesets, 450 files changed, 23340 insertions, 5216 deletions.
The three platforms that are added with the "soc" branch are here as
well, and we add some related machine files:
- For Aspeed AST2400/AST2500, we get the evaluation platform and the
Tyan Palmetto POWER8 mainboard that uses the AST2400 BMC
- For Oxnas 810SE, the Western Digital "My Book World Edition" is
added as the only platform at the moment.
- For ARM MPS2, the AN385 (Cortex-M3) and AN399 (Cortex-M7) are
supported
On the ARM Realview development platform, we now support all machines
with device tree, previously only the board files were supported,
which in turn will likely be removed soon.
Qualcomm IPQ4019 is the second generation ARM based "Internet
Processor", following the IPQ806x that is used in many high-end WiFi
routers. This one integrates two ath10k wifi radios that were
previously on separate chips.
Other boards that got added for existing chips are:
Ti OMAP family:
- Amazon Kindle Fire, first generation, tablet and ebook reader
- OnRISC Baltos iR 2110 and 3220 embedded industrial PCs
- TI AM5728 IDK, TI AM3359 ICE-V2, and TI DRA722 Rev C EVM
development systems
Samsung EXYNOS platform:
- Samsung ARTIK5 evaluation board, see
https://www.artik.io/modules/overview/artik-5/
NXP i.MX platforms:
- Ka-Ro electronics TX6S-8034, TX6S-8035, TX6U-8033, TX6U-81xx,
TX6Q-1036, TX6Q-1110/-1130, TXUL-0010 and TXUL-0011 industrial
SoM modules
- Embest MarS Board i.MX6Dual DIY platform
- Boundary Devices i.MX6 Quad Plus Nitrogen6_MAX and SoloX
Nitrogen6sx embedded boards
- Technexion Pico i.MX6UL compute module
- ZII VF610 Development Board
Marvell embedded (mvebu, orion, kirkwood) platforms:
- Linksys Viper (E4200v2 / EA4500) WiFi router
- Buffalo Kurobox Pro NAS
Qualcomm Snapdragon:
- Arrow DragonBoard 600c (96boards) with APQ8064 Snapdragon 600
Rockchips platform:
- mqmaker MiQi single-board computer
Altera SoCFPGA:
- samtec VIN|ING 1000 vehicle communication interface
Allwinner Sunxi platforms:
- Dserve DSRV9703C tablet
- Difrnce DIT4350 tablet
- Colorfly E708 Q1 tablet
- Polaroid MID2809PXE04 tablet
- Olimex A20 OLinuXino LIME2 single board computer
- Xunlong Orange Pi 2, Orange Pi One, and Orange Pi PC single board
computers
Across many platforms, bug fixes went in to address warnings that dtc
now emits with 'make dtbs W=1'. Further changes for device enablement
went into Ti OMAP, bcm283x (Raspberry Pi), bcm47xx (wifi router), Ti
Davinci, Samsung EXYNOS, Marvell mvebu/kirkwood/orion, NXP i.MX/Vybrid
NXP LPC18xx, NXP LPC32xx, Renesas shmobile/r-mobile/r-car, Rockchips
rk3xxx, ST Ux500, ST STi, Atmel AT91/SAMA5, Altera SoCFPGA, Allwinner
Sunxi, Sigma Designs Tango, NVIDIA Tegra, Socionext Uniphier and ARM
Versatile Express"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (458 commits)
ARM: dts: tango4: Import watchdog node
ARM: dts: tango4: Update cpus node for cpufreq
ARM: dts: tango4: Update DT to match clk driver
ARM: dts: tango4: Initial thermal support
arm/dst: Add Aspeed ast2500 device tree
arm/dts: Add Aspeed ast2400 device tree
ARM: sun7i: dt: Add pll3 and pll7 clocks
ARM: dts: sunxi: Add a olinuxino-lime2-emmc
ARM: dts: at91: sama5d4: add trng node
ARM: dts: at91: sama5d3: add trng node
ARM: dts: at91: sama5d2: add trng node
ARM: dts: at91: at91sam9g45 family: reduce the trng register map size
ARM: sun4i: dt: Add pll3 and pll7 clocks
ARM: sun5i: chip: Enable the TV Encoder
ARM: sun5i: r8: Add display blocks to the DTSI
ARM: sun5i: a13: Add display and TCON clocks
ARM: dts: ux500: configure the accelerometers open drain
ARM: mx5: dts: Enable USB OTG on M53EVK
ARM: dts: imx6ul-14x14-evk: Add audio support
ARM: dts: imx6qdl: Remove unneeded unit-addresses
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,9 @@ | ||
| Oxford Semiconductor OXNAS SoCs Family device tree bindings | ||
| ------------------------------------------- | ||
|
|
||
| Boards with the OX810SE SoC shall have the following properties: | ||
| Required root node property: | ||
| compatible: "oxsemi,ox810se" | ||
|
|
||
| Board compatible values: | ||
| - "wd,mbwe" (OX810SE) |
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70 changes: 46 additions & 24 deletions
70
Documentation/devicetree/bindings/interrupt-controller/nxp,lpc3220-mic.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -1,38 +1,60 @@ | ||
| * NXP LPC32xx Main Interrupt Controller | ||
| (MIC, including SIC1 and SIC2 secondary controllers) | ||
| * NXP LPC32xx MIC, SIC1 and SIC2 Interrupt Controllers | ||
|
|
||
| Required properties: | ||
| - compatible: Should be "nxp,lpc3220-mic" | ||
| - interrupt-controller: Identifies the node as an interrupt controller. | ||
| - interrupt-parent: Empty for the interrupt controller itself | ||
| - #interrupt-cells: The number of cells to define the interrupts. Should be 2. | ||
| The first cell is the IRQ number | ||
| The second cell is used to specify mode: | ||
| 1 = low-to-high edge triggered | ||
| 2 = high-to-low edge triggered | ||
| 4 = active high level-sensitive | ||
| 8 = active low level-sensitive | ||
| Default for internal sources should be set to 4 (active high). | ||
| - reg: Should contain MIC registers location and length | ||
| - compatible: "nxp,lpc3220-mic" or "nxp,lpc3220-sic". | ||
| - reg: should contain IC registers location and length. | ||
| - interrupt-controller: identifies the node as an interrupt controller. | ||
| - #interrupt-cells: the number of cells to define an interrupt, should be 2. | ||
| The first cell is the IRQ number, the second cell is used to specify | ||
| one of the supported IRQ types: | ||
| IRQ_TYPE_EDGE_RISING = low-to-high edge triggered, | ||
| IRQ_TYPE_EDGE_FALLING = high-to-low edge triggered, | ||
| IRQ_TYPE_LEVEL_HIGH = active high level-sensitive, | ||
| IRQ_TYPE_LEVEL_LOW = active low level-sensitive. | ||
| Reset value is IRQ_TYPE_LEVEL_LOW. | ||
|
|
||
| Optional properties: | ||
| - interrupt-parent: empty for MIC interrupt controller, link to parent | ||
| MIC interrupt controller for SIC1 and SIC2 | ||
| - interrupts: empty for MIC interrupt controller, cascaded MIC | ||
| hardware interrupts for SIC1 and SIC2 | ||
|
|
||
| Examples: | ||
| /* | ||
| * MIC | ||
| */ | ||
|
|
||
| /* LPC32xx MIC, SIC1 and SIC2 interrupt controllers */ | ||
| mic: interrupt-controller@40008000 { | ||
| compatible = "nxp,lpc3220-mic"; | ||
| reg = <0x40008000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
| }; | ||
|
|
||
| sic1: interrupt-controller@4000c000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x4000c000 0x4000>; | ||
| interrupt-controller; | ||
| interrupt-parent; | ||
| #interrupt-cells = <2>; | ||
| reg = <0x40008000 0xC000>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>, | ||
| <30 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* | ||
| * ADC | ||
| */ | ||
| sic2: interrupt-controller@40010000 { | ||
| compatible = "nxp,lpc3220-sic"; | ||
| reg = <0x40010000 0x4000>; | ||
| interrupt-controller; | ||
| #interrupt-cells = <2>; | ||
|
|
||
| interrupt-parent = <&mic>; | ||
| interrupts = <1 IRQ_TYPE_LEVEL_LOW>, | ||
| <31 IRQ_TYPE_LEVEL_LOW>; | ||
| }; | ||
|
|
||
| /* ADC */ | ||
| adc@40048000 { | ||
| compatible = "nxp,lpc3220-adc"; | ||
| reg = <0x40048000 0x1000>; | ||
| interrupt-parent = <&mic>; | ||
| interrupts = <39 4>; | ||
| interrupt-parent = <&sic1>; | ||
| interrupts = <7 IRQ_TYPE_LEVEL_HIGH>; | ||
| }; |
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48 changes: 48 additions & 0 deletions
48
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,48 @@ | ||
| DT bindings for the Renesas R-Car System Controller | ||
|
|
||
| == System Controller Node == | ||
|
|
||
| The R-Car System Controller provides power management for the CPU cores and | ||
| various coprocessors. | ||
|
|
||
| Required properties: | ||
| - compatible: Must contain exactly one of the following: | ||
| - "renesas,r8a7779-sysc" (R-Car H1) | ||
| - "renesas,r8a7790-sysc" (R-Car H2) | ||
| - "renesas,r8a7791-sysc" (R-Car M2-W) | ||
| - "renesas,r8a7792-sysc" (R-Car V2H) | ||
| - "renesas,r8a7793-sysc" (R-Car M2-N) | ||
| - "renesas,r8a7794-sysc" (R-Car E2) | ||
| - "renesas,r8a7795-sysc" (R-Car H3) | ||
| - reg: Address start and address range for the device. | ||
| - #power-domain-cells: Must be 1. | ||
|
|
||
|
|
||
| Example: | ||
|
|
||
| sysc: system-controller@e6180000 { | ||
| compatible = "renesas,r8a7791-sysc"; | ||
| reg = <0 0xe6180000 0 0x0200>; | ||
| #power-domain-cells = <1>; | ||
| }; | ||
|
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||
|
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||
| == PM Domain Consumers == | ||
|
|
||
| Devices residing in a power area must refer to that power area, as documented | ||
| by the generic PM domain bindings in | ||
| Documentation/devicetree/bindings/power/power_domain.txt. | ||
|
|
||
| Required properties: | ||
| - power-domains: A phandle and symbolic PM domain specifier, as defined in | ||
| <dt-bindings/power/r8a77*-sysc.h>. | ||
|
|
||
|
|
||
| Example: | ||
|
|
||
| L2_CA15: cache-controller@0 { | ||
| compatible = "cache"; | ||
| power-domains = <&sysc R8A7791_PD_CA15_SCU>; | ||
| cache-unified; | ||
| cache-level = <2>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,21 @@ | ||
| MediaTek AUXADC | ||
| =============== | ||
|
|
||
| The Auxiliary Analog/Digital Converter (AUXADC) is an ADC found | ||
| in some Mediatek SoCs which among other things measures the temperatures | ||
| in the SoC. It can be used directly with register accesses, but it is also | ||
| used by thermal controller which reads the temperatures from the AUXADC | ||
| directly via its own bus interface. See | ||
| Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | ||
| for the Thermal Controller which holds a phandle to the AUXADC. | ||
|
|
||
| Required properties: | ||
| - compatible: Must be "mediatek,mt8173-auxadc" | ||
| - reg: Address range of the AUXADC unit | ||
|
|
||
| Example: | ||
|
|
||
| auxadc: auxadc@11001000 { | ||
| compatible = "mediatek,mt8173-auxadc"; | ||
| reg = <0 0x11001000 0 0x1000>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
| @@ -0,0 +1,35 @@ | ||
| * Rockchip General Register Files (GRF) | ||
|
|
||
| The general register file will be used to do static set by software, which | ||
| is composed of many registers for system control. | ||
|
|
||
| From RK3368 SoCs, the GRF is divided into two sections, | ||
| - GRF, used for general non-secure system, | ||
| - PMUGRF, used for always on system | ||
|
|
||
| Required Properties: | ||
|
|
||
| - compatible: GRF should be one of the followings | ||
| - "rockchip,rk3066-grf", "syscon": for rk3066 | ||
| - "rockchip,rk3188-grf", "syscon": for rk3188 | ||
| - "rockchip,rk3228-grf", "syscon": for rk3228 | ||
| - "rockchip,rk3288-grf", "syscon": for rk3288 | ||
| - "rockchip,rk3368-grf", "syscon": for rk3368 | ||
| - "rockchip,rk3399-grf", "syscon": for rk3399 | ||
| - compatible: PMUGRF should be one of the followings | ||
| - "rockchip,rk3368-pmugrf", "syscon": for rk3368 | ||
| - "rockchip,rk3399-pmugrf", "syscon": for rk3399 | ||
| - reg: physical base address of the controller and length of memory mapped | ||
| region. | ||
|
|
||
| Example: GRF and PMUGRF of RK3399 SoCs | ||
|
|
||
| pmugrf: syscon@ff320000 { | ||
| compatible = "rockchip,rk3399-pmugrf", "syscon"; | ||
| reg = <0x0 0xff320000 0x0 0x1000>; | ||
| }; | ||
|
|
||
| grf: syscon@ff770000 { | ||
| compatible = "rockchip,rk3399-grf", "syscon"; | ||
| reg = <0x0 0xff770000 0x0 0x10000>; | ||
| }; |
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