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Merge drm/drm-next into drm-intel-next-queued
Backmerging to pull in HDR DP code: https://lists.freedesktop.org/archives/dri-devel/2019-September/236453.html Signed-off-by: Joonas Lahtinen <[email protected]>
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@@ -751,7 +751,7 @@ S: Santa Cruz, California | |
S: USA | ||
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N: Luis Correia | ||
E: [email protected] | ||
E: [email protected] | ||
D: Ralink rt2x00 WLAN driver | ||
S: Belas, Portugal | ||
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@@ -2,7 +2,7 @@ What: /sys/bus/w1/devices/.../pio | |
Date: May 2012 | ||
Contact: Markus Franke <[email protected]> | ||
Description: read/write the contents of the two PIO's of the DS28E04-100 | ||
see Documentation/w1/slaves/w1_ds28e04 for detailed information | ||
see Documentation/w1/slaves/w1_ds28e04.rst for detailed information | ||
Users: any user space application which wants to communicate with DS28E04-100 | ||
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@@ -11,5 +11,5 @@ What: /sys/bus/w1/devices/.../eeprom | |
Date: May 2012 | ||
Contact: Markus Franke <[email protected]> | ||
Description: read/write the contents of the EEPROM memory of the DS28E04-100 | ||
see Documentation/w1/slaves/w1_ds28e04 for detailed information | ||
see Documentation/w1/slaves/w1_ds28e04.rst for detailed information | ||
Users: any user space application which wants to communicate with DS28E04-100 |
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@@ -2,5 +2,5 @@ What: /sys/bus/w1/devices/.../w1_seq | |
Date: Apr 2015 | ||
Contact: Matt Campbell <[email protected]> | ||
Description: Support for the DS28EA00 chain sequence function | ||
see Documentation/w1/slaves/w1_therm for detailed information | ||
see Documentation/w1/slaves/w1_therm.rst for detailed information | ||
Users: any user space application which wants to communicate with DS28EA00 |
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@@ -0,0 +1,50 @@ | ||
What: /sys/kernel/debug/hisi_zip/<bdf>/comp_core[01]/regs | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: Dump of compression cores related debug registers. | ||
Only available for PF. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/decomp_core[0-5]/regs | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: Dump of decompression cores related debug registers. | ||
Only available for PF. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/clear_enable | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: Compression/decompression core debug registers read clear | ||
control. 1 means enable register read clear, otherwise 0. | ||
Writing to this file has no functional effect, only enable or | ||
disable counters clear after reading of these registers. | ||
Only available for PF. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/current_qm | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: One ZIP controller has one PF and multiple VFs, each function | ||
has a QM. Select the QM which below qm refers to. | ||
Only available for PF. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/qm_regs | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: Dump of QM related debug registers. | ||
Available for PF and VF in host. VF in guest currently only | ||
has one debug register. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/current_q | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: One QM may contain multiple queues. Select specific queue to | ||
show its debug registers in above qm_regs. | ||
Only available for PF. | ||
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What: /sys/kernel/debug/hisi_zip/<bdf>/qm/clear_enable | ||
Date: Nov 2018 | ||
Contact: [email protected] | ||
Description: QM debug registers(qm_regs) read clear control. 1 means enable | ||
register read clear, otherwise 0. | ||
Writing to this file has no functional effect, only enable or | ||
disable counters clear after reading of these registers. | ||
Only available for PF. |
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@@ -0,0 +1,23 @@ | ||
What: /sys/kernel/debug/moxtet/input | ||
Date: March 2019 | ||
KernelVersion: 5.3 | ||
Contact: Marek Behún <[email protected]> | ||
Description: (R) Read input from the shift registers, in hexadecimal. | ||
Returns N+1 bytes, where N is the number of Moxtet connected | ||
modules. The first byte is from the CPU board itself. | ||
Example: 101214 | ||
10: CPU board with SD card | ||
12: 2 = PCIe module, 1 = IRQ not active | ||
14: 4 = Peridot module, 1 = IRQ not active | ||
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What: /sys/kernel/debug/moxtet/output | ||
Date: March 2019 | ||
KernelVersion: 5.3 | ||
Contact: Marek Behún <[email protected]> | ||
Description: (RW) Read last written value to the shift registers, in | ||
hexadecimal, or write values to the shift registers, also | ||
in hexadecimal. | ||
Example: 0102 | ||
01: 01 was last written, or is to be written, to the | ||
first module's shift register | ||
02: the same for second module |
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@@ -91,29 +91,6 @@ Description: | |
When counting down the counter start from preset value | ||
and fire event when reach 0. | ||
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What: /sys/bus/iio/devices/iio:deviceX/in_count_quadrature_mode_available | ||
KernelVersion: 4.12 | ||
Contact: [email protected] | ||
Description: | ||
Reading returns the list possible quadrature modes. | ||
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What: /sys/bus/iio/devices/iio:deviceX/in_count0_quadrature_mode | ||
KernelVersion: 4.12 | ||
Contact: [email protected] | ||
Description: | ||
Configure the device counter quadrature modes: | ||
channel_A: | ||
Encoder A input servers as the count input and B as | ||
the UP/DOWN direction control input. | ||
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channel_B: | ||
Encoder B input serves as the count input and A as | ||
the UP/DOWN direction control input. | ||
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quadrature: | ||
Encoder A and B inputs are mixed to get direction | ||
and count with a scale of 0.25. | ||
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What: /sys/bus/iio/devices/iio:deviceX/in_count_enable_mode_available | ||
KernelVersion: 4.12 | ||
Contact: [email protected] | ||
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