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Commits on Jun 18, 2021

• cxl/pci: Rename CXL REGLOC ID

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  Ben Widawsky

  authored and

  djbw

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  4ad6181

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• cxl/acpi: Use the ACPI CFMWS to create static decoder objects

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  AlisonSchofield

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  djbw

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• cxl/acpi: Add the Host Bridge base address to CXL port objects

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  AlisonSchofield

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  djbw

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Commits on Jun 15, 2021

• cxl/pmem: Register 'pmem' / cxl_nvdimm devices

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  djbw

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• cxl/pmem: Add initial infrastructure for pmem support

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• cxl/core: Add cxl-bus driver infrastructure

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  djbw

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• cxl/pci: Add media provisioning required commands

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  Ben Widawsky

  authored and

  djbw

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Commits on Jun 12, 2021

• cxl/component_regs: Fix offset

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  Ben Widawsky

  authored and

  djbw

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  ba26864

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• cxl/hdm: Fix decoder count calculation

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  Ben Widawsky

  authored and

  djbw

  committed
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Commits on Jun 10, 2021

• cxl/acpi: Introduce cxl_decoder objects

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  djbw

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• cxl/acpi: Enumerate host bridge root ports

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  djbw

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• cxl/acpi: Add downstream port data to cxl_port instances

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• cxl/Kconfig: Default drivers to CONFIG_CXL_BUS

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  djbw

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• cxl/acpi: Introduce the root of a cxl_port topology

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Commits on Jun 6, 2021

• cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'

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  djbw

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• cxl/pci: Add HDM decoder capabilities

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  Ben Widawsky

  authored and

  djbw

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• cxl/pci: Reserve individual register block regions

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  weiny2

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• cxl/pci: Map registers based on capabilities

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  weiny2

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• cxl/pci: Reserve all device regions at once

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  weiny2

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• cxl/pci: Introduce cxl_decode_register_block()

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  weiny2

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Commits on May 26, 2021

• cxl/mem: Get rid of @cxlm.base

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  Ben Widawsky

  authored and

  djbw

  committed
  6630d31

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• cxl/mem: Move register locator logic into reg setup

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  Ben Widawsky

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  djbw

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• cxl/mem: Split creation from mapping in probe

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  Ben Widawsky

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  djbw

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• cxl/mem: Use dev instead of pdev->dev

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  Ben Widawsky

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  djbw

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• cxl/mem: Demarcate vendor specific capability IDs

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  Ben Widawsky

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  djbw

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• cxl/pci.c: Add a 'label_storage_size' attribute to the memdev

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  stellarhopper

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• cxl: Rename mem to pci

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  Ben Widawsky

  authored and

  djbw

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Commits on May 14, 2021

• cxl/core: Refactor CXL register lookup for bridge reuse

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  djbw

  committed
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• cxl/core: Rename bus.c to core.c

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  djbw

  committed
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• cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices

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  djbw

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• cxl/mem: Move some definitions to mem.h

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Commits on Apr 17, 2021

• cxl/mem: Fix memory device capacity probing

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  djbw

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Commits on Apr 16, 2021

• cxl/mem: Fix register block offset calculation

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  Ben Widawsky

  authored and

  djbw

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Commits on Apr 6, 2021

• cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAX

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  Robert Richter

  authored and

  djbw

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  392be0b

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• cxl/mem: Disable cxl device power management

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