Merge pull request openhwgroup#38 from Silabs-ArjanB/ArjanB_pmp_removal

Conditionally removed PMP documentation
andreaskurth · May 21, 2020 · b1350a7 · b1350a7
2 parents 55d9697 + 1552ecb
commit b1350a7
Show file tree

Hide file tree

Showing 3 changed files with 39 additions and 34 deletions.
diff --git a/cores/cv32e40p/user_manual/source/control_status_registers.rst b/cores/cv32e40p/user_manual/source/control_status_registers.rst
@@ -377,38 +377,39 @@ Reset Value: Defined
 
 Table 10: MHARTID
 
-PMP Configuration (PMPCFGx)
----------------------------
+.. only:: PMP
 
-CSR Address: 0x3A{0,1,2,3}
+  PMP Configuration (PMPCFGx)
+  ---------------------------
 
-Reset Value: 0x0000_0000
+  CSR Address: 0x3A{0,1,2,3}
 
-+----------+
-| 31 : 0   |
-+==========+
-| PMPCFGx  |
-+----------+
+  Reset Value: 0x0000_0000
 
-If the PMP is enabled, these four registers contain the configuration of
-the PMP as specified by the official privileged spec 1.10.
+  +----------+
+  | 31 : 0   |
+  +==========+
+  | PMPCFGx  |
+  +----------+
 
-PMP Address (PMPADDRx)
-----------------------
+  If the PMP is enabled, these four registers contain the configuration of
+  the PMP as specified by the official privileged spec 1.10.
 
-CSR Address: 0x3B{0x0, 0x1, …. 0xF}
+  PMP Address (PMPADDRx)
+  ----------------------
 
-Reset Value: 0x0000_0000
+  CSR Address: 0x3B{0x0, 0x1, …. 0xF}
 
-+----------+
-| 31 : 0   |
-+==========+
-| PMPADDRx |
-+----------+
+  Reset Value: 0x0000_0000
 
+  +----------+
+  | 31 : 0   |
+  +==========+
+  | PMPADDRx |
+  +----------+
 
-If the PMP is enabled, these sixteen registers contain the addresses of
-the PMP as specified by the official privileged spec 1.10.
+  If the PMP is enabled, these sixteen registers contain the addresses of
+  the PMP as specified by the official privileged spec 1.10.
 
 Debug Control and Status (DCSR)
 -------------------------------

diff --git a/cores/cv32e40p/user_manual/source/intro.rst b/cores/cv32e40p/user_manual/source/intro.rst
@@ -127,7 +127,7 @@ Document Revisions
 ------------------
 
 | March 2020
-| Revision 4.4
+| Revision 4.7
 
 +--------+------------+--------------------+--------------------------------------------------------------------------------------------------+
 | Rev.   | Date       | Author             | Description                                                                                      |
@@ -174,4 +174,6 @@ Document Revisions
 +--------+------------+--------------------+--------------------------------------------------------------------------------------------------+
 | 4.4    | 30.03.20   | A. Bink            | Fixed MIEX, MTVECX, MIPX CSR addresses and added description for MIPX, MTVECX, MIEX, MIP, MIE.   |
 +--------+------------+--------------------+--------------------------------------------------------------------------------------------------+
+| 4.7    | 06.05.20   | A. Bink            | (Conditionally) removed PMP-related documentation                                                |
++--------+------------+--------------------+--------------------------------------------------------------------------------------------------+
 
diff --git a/cores/cv32e40p/user_manual/source/load_store_unit.rst b/cores/cv32e40p/user_manual/source/load_store_unit.rst
@@ -80,17 +80,6 @@ protocol.
 
    Figure 4: Slow Response Memory Transaction
 
-Physical Memory Protection (PMP) Unit
--------------------------------------
-
-The CV32E40P core has a PMP module which can be enabled by setting the
-parameter PULP_SECURE=1 which also enabled the core to possibly run in
-USER MODE. Such unit has a configurable number of entries (up to 16) and
-supports all the modes as TOR, NAPOT and NA4. Every fetch, load and
-store access executed in USER MODE are first filtered by the PMP unit
-which can possibly generated exceptions. For the moment, the MPRV bit in
-MSTATUS as well as the LOCK mechanism in the PMP are not supported.
-
 Post-Incrementing Load and Store Instructions
 ---------------------------------------------
 
@@ -106,3 +95,16 @@ instructions allow the address increment to be embedded in the memory
 access instructions and get rid of separate instructions to handle
 pointers. Coupled with hardware loop extension, this instructions allow
 to reduce the loop overhead significantly.
+
+.. only:: PMP
+
+  Physical Memory Protection (PMP) Unit
+  -------------------------------------
+
+  The CV32E40P core has a PMP module which can be enabled by setting the
+  parameter PULP_SECURE=1 which also enabled the core to possibly run in
+  USER MODE. Such unit has a configurable number of entries (up to 16) and
+  supports all the modes as TOR, NAPOT and NA4. Every fetch, load and
+  store access executed in USER MODE are first filtered by the PMP unit
+  which can possibly generated exceptions. For the moment, the MPRV bit in
+  MSTATUS as well as the LOCK mechanism in the PMP are not supported.