OpenTitan: Open source silicon root of trust

Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

Generic Register Interface (contains various adapters)

Package manager and build abstraction tool for FPGA/ASIC development

A SystemVerilog source file pickler.

RISC-V Debug Support for our PULP RISC-V Cores

A demo system for Ibex including debug support and some peripherals

Side-channel analysis setup for OpenTitan

PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

A List of Free and Open Source Hardware Verification Tools and Frameworks

Documentation for the OpenHW Group's set of CORE-V RISC-V cores

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Network on Chip Simulator

Contains JSON description of pulp configurations

SpinalHDL core

HDL compiler based on LLHD