IC design and development should be faster，simpler and more reliable

RTL, Cmodel, and testbench for NVDLA

Verilog AXI components for FPGA implementation

Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip …

使用Verilog实现的CNN模块，可以方便的在FPGA项目中使用

Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database

CNN acceleration on virtex-7 FPGA with verilog HDL

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end produ…

Verilog Generator of Neural Net Digit Detector for FPGA

Opensource DDR3 Controller

SD-Card controller, using either SPI, SDIO, or eMMC interfaces

Implementation of CNN using Verilog

IC implementation of Systolic Array for TPU

Convolutional accelerator kernel, target ASIC & FPGA

FPGA based acceleration of Convolutional Neural Networks. The project is developed by Verilog for Altera DE5 Net platform.

Deep Learning Accelerator (Convolution Neural Networks)

ODIN online-learning digital spiking neural network (SNN) processor - HDL source code and documentation.

This is a fully parameterized verilog implementation of computation kernels for accleration of the Inference of Convolutional Neural Networks on FPGAs

Verilog module for calculation of FFT.

Generator of verilog description for FPGA MobileNet implementation

A convolutional neural network implemented in hardware (verilog)

You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size of the systolic array can be changed, now it is 16X16.

2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。

This repository hosts the code for an FPGA based accelerator for convolutional neural networks

Fully opensource spiking neural network accelerator

Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.

Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…

hardware design of universal NPU(CNN accelerator) for various convolution neural network