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AC
ADPLL
BNN
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FPGA/ASIC
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Code of my Bachelor's thesis on Brain-Computer-Interfaces, Deep Transfer Learning with CNNs, Hyperdimensional Computing and EEG data processing.
A K-I-S-S library for Hyperdimensional Computing on MSP430 ultra-low-power MCU.
This project aims to classify News articles using hyperdimensional (HD) computing in OpenCL
HDCpy: An easy-to-use Python library for Hyperdimensional Computing (HDC) research.
Hyperdimensional computing similarity check. Engine made using HLS.
Combination of hyperdimensional computing with neural networks
TactileHD: a tactile preception framework based on hyperdimensional (HD) computing
Text classification algorithm using hyperdimensional computing
A implemention of Hyperdimensional Computing for CARDIO
Libraries for applying sparsification recipes to neural networks with a few lines of code, enabling faster and smaller models
BSQ: Exploring Bit-Level Sparsity for Mixed-Precision Neural Network Quantization (ICLR 2021)
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversi…
My learning notes/codes for ML SYS.
PyTorch implementation of FractalGen https://arxiv.org/abs/2502.17437
Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.
Generator of verilog description for FPGA MobileNet implementation
High Granularity Quantizarion for Ultra-Fast Machine Learning Applications on FPGAs
Verilog Generator of Neural Net Digit Detector for FPGA
This project is a custom hardware accelerator based on the RISC-V architecture designed to optimize K-Nearest Neighbors (KNN) operations. The accelerator includes several modules such as the Instru…
Working 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
This repository includes the verilog codes written in Seoul National University Hardware System Design class. Professor Sungjoo Yoo, Seoul National University: https://www.aminer.org/profile/sungjo…
This project is a custom hardware accelerator based on the RISC-V architecture designed to optimize K-Nearest Neighbors (KNN) operations. The accelerator includes several modules such as the Instru…
A simplified replica of the Eyeriss AI accelerator coded in Verilog