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Fix a bunch of custom-inserter functions to handle the case where
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the pseudo instruction is not at the end of the block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107655 91177308-0d34-0410-b5e6-96231b3b80d8
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Dan Gohman committed Jul 6, 2010
1 parent 7d26218 commit b81c771
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Showing 14 changed files with 274 additions and 209 deletions.
5 changes: 5 additions & 0 deletions include/llvm/CodeGen/MachineBasicBlock.h
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Original file line number Diff line number Diff line change
Expand Up @@ -259,6 +259,11 @@ class MachineBasicBlock : public ilist_node<MachineBasicBlock> {
/// machine basic block (i.e., copies all the successors fromMBB and
/// remove all the successors from fromMBB).
void transferSuccessors(MachineBasicBlock *fromMBB);

/// transferSuccessorsAndUpdatePHIs - Transfers all the successors, as
/// in transferSuccessors, and update PHI operands in the successor blocks
/// which refer to fromMBB to refer to this.
void transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB);

/// isSuccessor - Return true if the specified MBB is a successor of this
/// block.
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30 changes: 25 additions & 5 deletions lib/CodeGen/MachineBasicBlock.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -335,12 +335,32 @@ void MachineBasicBlock::transferSuccessors(MachineBasicBlock *fromMBB) {
if (this == fromMBB)
return;

for (MachineBasicBlock::succ_iterator I = fromMBB->succ_begin(),
E = fromMBB->succ_end(); I != E; ++I)
addSuccessor(*I);
while (!fromMBB->succ_empty()) {
MachineBasicBlock *Succ = *fromMBB->succ_begin();
addSuccessor(Succ);
fromMBB->removeSuccessor(Succ);
}
}

void
MachineBasicBlock::transferSuccessorsAndUpdatePHIs(MachineBasicBlock *fromMBB) {
if (this == fromMBB)
return;

while (!fromMBB->succ_empty())
fromMBB->removeSuccessor(fromMBB->succ_begin());
while (!fromMBB->succ_empty()) {
MachineBasicBlock *Succ = *fromMBB->succ_begin();
addSuccessor(Succ);
fromMBB->removeSuccessor(Succ);

// Fix up any PHI nodes in the successor.
for (MachineBasicBlock::iterator MI = Succ->begin(), ME = Succ->end();
MI != ME && MI->isPHI(); ++MI)
for (unsigned i = 2, e = MI->getNumOperands()+1; i != e; i += 2) {
MachineOperand &MO = MI->getOperand(i);
if (MO.getMBB() == fromMBB)
MO.setMBB(this);
}
}
}

bool MachineBasicBlock::isSuccessor(const MachineBasicBlock *MBB) const {
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52 changes: 31 additions & 21 deletions lib/Target/ARM/ARMISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3637,7 +3637,12 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
MF->insert(It, loop1MBB);
MF->insert(It, loop2MBB);
MF->insert(It, exitMBB);
exitMBB->transferSuccessors(BB);

// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
exitMBB->transferSuccessorsAndUpdatePHIs(BB);

// thisMBB:
// ...
Expand Down Expand Up @@ -3675,7 +3680,7 @@ ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
// ...
BB = exitMBB;

MF->DeleteMachineInstr(MI); // The instruction is gone now.
MI->eraseFromParent(); // The instruction is gone now.

return BB;
}
Expand Down Expand Up @@ -3718,7 +3723,12 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB);
MF->insert(It, loopMBB);
MF->insert(It, exitMBB);
exitMBB->transferSuccessors(BB);

// Transfer the remainder of BB and its successor edges to exitMBB.
exitMBB->splice(exitMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
exitMBB->transferSuccessorsAndUpdatePHIs(BB);

MachineRegisterInfo &RegInfo = MF->getRegInfo();
unsigned scratch = RegInfo.createVirtualRegister(ARM::GPRRegisterClass);
Expand Down Expand Up @@ -3763,7 +3773,7 @@ ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
// ...
BB = exitMBB;

MF->DeleteMachineInstr(MI); // The instruction is gone now.
MI->eraseFromParent(); // The instruction is gone now.

return BB;
}
Expand Down Expand Up @@ -3848,22 +3858,21 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
.addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());
F->insert(It, copy0MBB);
F->insert(It, sinkMBB);
// Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
E = BB->succ_end(); I != E; ++I)
sinkMBB->addSuccessor(*I);
// Next, remove all successors of the current block, and add the true
// and fallthrough blocks as its successors.
while (!BB->succ_empty())
BB->removeSuccessor(BB->succ_begin());

// Transfer the remainder of BB and its successor edges to sinkMBB.
sinkMBB->splice(sinkMBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);

BB->addSuccessor(copy0MBB);
BB->addSuccessor(sinkMBB);

BuildMI(BB, dl, TII->get(ARM::tBcc)).addMBB(sinkMBB)
.addImm(MI->getOperand(3).getImm()).addReg(MI->getOperand(4).getReg());

// copy0MBB:
// %FalseValue = ...
// # fallthrough to sinkMBB
Expand All @@ -3876,11 +3885,12 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = sinkMBB;
BuildMI(BB, dl, TII->get(ARM::PHI), MI->getOperand(0).getReg())
BuildMI(*BB, BB->begin(), dl,
TII->get(ARM::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);

F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}

Expand All @@ -3901,7 +3911,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(SrcReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVtgpr2gpr : ARM::tMOVgpr2gpr;
BuildMI(BB, dl, TII->get(CopyOpc), ARM::SP)
BuildMI(*BB, MI, dl, TII->get(CopyOpc), ARM::SP)
.addReg(SrcReg, getKillRegState(SrcIsKill));
}

Expand Down Expand Up @@ -3933,7 +3943,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
NeedPred = true; NeedCC = true; NeedOp3 = true;
break;
}
MachineInstrBuilder MIB = BuildMI(BB, dl, TII->get(OpOpc), ARM::SP);
MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(OpOpc), ARM::SP);
if (OpOpc == ARM::tAND)
AddDefaultT1CC(MIB);
MIB.addReg(ARM::SP);
Expand All @@ -3949,10 +3959,10 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(DstReg);
unsigned CopyOpc = (RC == ARM::tGPRRegisterClass)
? ARM::tMOVgpr2tgpr : ARM::tMOVgpr2gpr;
BuildMI(BB, dl, TII->get(CopyOpc))
BuildMI(*BB, MI, dl, TII->get(CopyOpc))
.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead))
.addReg(ARM::SP);
MF->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
}
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7 changes: 5 additions & 2 deletions lib/Target/Alpha/AlphaISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -863,7 +863,10 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock *llscMBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);

sinkMBB->transferSuccessors(thisMBB);
sinkMBB->splice(sinkMBB->begin(), thisMBB,
llvm::next(MachineBasicBlock::iterator(MI)),
thisMBB->end());
sinkMBB->transferSuccessorsAndUpdatePHIs(thisMBB);

F->insert(It, llscMBB);
F->insert(It, sinkMBB);
Expand Down Expand Up @@ -912,7 +915,7 @@ AlphaTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
thisMBB->addSuccessor(llscMBB);
llscMBB->addSuccessor(llscMBB);
llscMBB->addSuccessor(sinkMBB);
F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.

return sinkMBB;
}
Expand Down
70 changes: 33 additions & 37 deletions lib/Target/MBlaze/MBlazeISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -234,6 +234,24 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineRegisterInfo &R = F->getRegInfo();
MachineBasicBlock *loop = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *finish = F->CreateMachineBasicBlock(LLVM_BB);
F->insert(It, loop);
F->insert(It, finish);

// Update machine-CFG edges by transfering adding all successors and
// remaining instructions from the current block to the new block which
// will contain the Phi node for the select.
finish->splice(finish->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
finish->transferSuccessorsAndUpdatePHIs(BB);

// Add the true and fallthrough blocks as its successors.
BB->addSuccessor(loop);
BB->addSuccessor(finish);

// Next, add the finish block as a successor of the loop block
loop->addSuccessor(finish);
loop->addSuccessor(loop);

unsigned IAMT = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
BuildMI(BB, dl, TII->get(MBlaze::ANDI), IAMT)
Expand All @@ -249,26 +267,6 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
.addReg(IAMT)
.addMBB(finish);

F->insert(It, loop);
F->insert(It, finish);

// Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
e = BB->succ_end(); i != e; ++i)
finish->addSuccessor(*i);

// Next, remove all successors of the current block, and add the true
// and fallthrough blocks as its successors.
while(!BB->succ_empty())
BB->removeSuccessor(BB->succ_begin());
BB->addSuccessor(loop);
BB->addSuccessor(finish);

// Next, add the finish block as a successor of the loop block
loop->addSuccessor(finish);
loop->addSuccessor(loop);

unsigned DST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
unsigned NDST = R.createVirtualRegister(MBlaze::CPURegsRegisterClass);
BuildMI(loop, dl, TII->get(MBlaze::PHI), DST)
Expand Down Expand Up @@ -298,12 +296,13 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
.addReg(NAMT)
.addMBB(loop);

BuildMI(finish, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
BuildMI(*finish, finish->begin(), dl,
TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
.addReg(IVAL).addMBB(BB)
.addReg(NDST).addMBB(loop);

// The pseudo instruction is no longer needed so remove it
F->DeleteMachineInstr(MI);
MI->eraseFromParent();
return finish;
}

Expand Down Expand Up @@ -338,39 +337,36 @@ MBlazeTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
case MBlazeCC::LE: Opc = MBlaze::BGTID; break;
}

BuildMI(BB, dl, TII->get(Opc))
.addReg(MI->getOperand(3).getReg())
.addMBB(dneBB);

F->insert(It, flsBB);
F->insert(It, dneBB);

// Update machine-CFG edges by first adding all successors of the current
// block to the new block which will contain the Phi node for the select.
for(MachineBasicBlock::succ_iterator i = BB->succ_begin(),
e = BB->succ_end(); i != e; ++i)
dneBB->addSuccessor(*i);
// Transfer the remainder of BB and its successor edges to dneBB.
dneBB->splice(dneBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
dneBB->transferSuccessorsAndUpdatePHIs(BB);

// Next, remove all successors of the current block, and add the true
// and fallthrough blocks as its successors.
while(!BB->succ_empty())
BB->removeSuccessor(BB->succ_begin());
BB->addSuccessor(flsBB);
BB->addSuccessor(dneBB);
flsBB->addSuccessor(dneBB);

BuildMI(BB, dl, TII->get(Opc))
.addReg(MI->getOperand(3).getReg())
.addMBB(dneBB);

// sinkMBB:
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
//BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
// .addReg(MI->getOperand(1).getReg()).addMBB(flsBB)
// .addReg(MI->getOperand(2).getReg()).addMBB(BB);

BuildMI(dneBB, dl, TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
BuildMI(*dneBB, dneBB->begin(), dl,
TII->get(MBlaze::PHI), MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(flsBB)
.addReg(MI->getOperand(1).getReg()).addMBB(BB);

F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.
return dneBB;
}
}
Expand Down
25 changes: 16 additions & 9 deletions lib/Target/MSP430/MSP430ISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1070,7 +1070,10 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,

// Update machine-CFG edges by transferring all successors of the current
// block to the block containing instructions after shift.
RemBB->transferSuccessors(BB);
RemBB->splice(RemBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
RemBB->transferSuccessorsAndUpdatePHIs(BB);

// Add adges BB => LoopBB => RemBB, BB => RemBB, LoopBB => LoopBB
BB->addSuccessor(LoopBB);
Expand Down Expand Up @@ -1116,11 +1119,11 @@ MSP430TargetLowering::EmitShiftInstr(MachineInstr *MI,

// RemBB:
// DestReg = phi [%SrcReg, BB], [%ShiftReg, LoopBB]
BuildMI(RemBB, dl, TII.get(MSP430::PHI), DstReg)
BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
.addReg(SrcReg).addMBB(BB)
.addReg(ShiftReg2).addMBB(LoopBB);

F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.
return RemBB;
}

Expand Down Expand Up @@ -1158,18 +1161,22 @@ MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
MachineFunction *F = BB->getParent();
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
BuildMI(BB, dl, TII.get(MSP430::JCC))
.addMBB(copy1MBB)
.addImm(MI->getOperand(3).getImm());
F->insert(I, copy0MBB);
F->insert(I, copy1MBB);
// Update machine-CFG edges by transferring all successors of the current
// block to the new block which will contain the Phi node for the select.
copy1MBB->transferSuccessors(BB);
copy1MBB->splice(copy1MBB->begin(), BB,
llvm::next(MachineBasicBlock::iterator(MI)),
BB->end());
copy1MBB->transferSuccessorsAndUpdatePHIs(BB);
// Next, add the true and fallthrough blocks as its successors.
BB->addSuccessor(copy0MBB);
BB->addSuccessor(copy1MBB);

BuildMI(BB, dl, TII.get(MSP430::JCC))
.addMBB(copy1MBB)
.addImm(MI->getOperand(3).getImm());

// copy0MBB:
// %FalseValue = ...
// # fallthrough to copy1MBB
Expand All @@ -1182,11 +1189,11 @@ MSP430TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
// %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
// ...
BB = copy1MBB;
BuildMI(BB, dl, TII.get(MSP430::PHI),
BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI),
MI->getOperand(0).getReg())
.addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
.addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);

F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
MI->eraseFromParent(); // The pseudo instruction is gone now.
return BB;
}
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