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[AArch64] Add support for Samsung Exynos-M1
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Adds core tuning support for new Samsung Exynos-M1 core (ARMv8-A).

Differential Revision: http://reviews.llvm.org/D15663

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@256828 91177308-0d34-0410-b5e6-96231b3b80d8
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MinSeong Kim committed Jan 5, 2016
1 parent 176a9b2 commit eaca36f
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Showing 8 changed files with 67 additions and 2 deletions.
1 change: 1 addition & 0 deletions include/llvm/Support/ARMTargetParser.def
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Expand Up @@ -213,6 +213,7 @@ ARM_CPU_NAME("cortex-a53", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, true, AEK_CRC)
ARM_CPU_NAME("cortex-a57", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
ARM_CPU_NAME("cortex-a72", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
ARM_CPU_NAME("cyclone", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
ARM_CPU_NAME("exynos-m1", AK_ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, AEK_CRC)
// Non-standard Arch names.
ARM_CPU_NAME("iwmmxt", AK_IWMMXT, FK_NONE, true, AEK_NONE)
ARM_CPU_NAME("xscale", AK_XSCALE, FK_NONE, true, AEK_NONE)
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10 changes: 10 additions & 0 deletions lib/Target/AArch64/AArch64.td
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Expand Up @@ -124,6 +124,14 @@ def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone",
FeaturePerfMon,
FeatureZCRegMove, FeatureZCZeroing]>;

def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M1 processors",
[FeatureFPARMv8,
FeatureNEON,
FeatureCrypto,
FeatureCRC,
FeaturePerfMon]>;

def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8,
FeatureNEON,
FeatureCRC,
Expand All @@ -136,6 +144,8 @@ def : ProcessorModel<"cortex-a57", CortexA57Model, [ProcA57]>;
// FIXME: Cortex-A72 is currently modelled as an Cortex-A57.
def : ProcessorModel<"cortex-a72", CortexA57Model, [ProcA57]>;
def : ProcessorModel<"cyclone", CycloneModel, [ProcCyclone]>;
// FIXME: Exynos-M1 is currently modelled without a specific SchedModel.
def : ProcessorModel<"exynos-m1", NoSchedModel, [ProcExynosM1]>;

//===----------------------------------------------------------------------===//
// Assembly parser
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10 changes: 9 additions & 1 deletion lib/Target/AArch64/AArch64Subtarget.h
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Expand Up @@ -33,7 +33,14 @@ class Triple;

class AArch64Subtarget : public AArch64GenSubtargetInfo {
protected:
enum ARMProcFamilyEnum {Others, CortexA35, CortexA53, CortexA57, Cyclone};
enum ARMProcFamilyEnum {
Others,
CortexA35,
CortexA53,
CortexA57,
Cyclone,
ExynosM1
};

/// ARMProcFamily - ARM processor family: Cortex-A53, Cortex-A57, and others.
ARMProcFamilyEnum ARMProcFamily;
Expand Down Expand Up @@ -143,6 +150,7 @@ class AArch64Subtarget : public AArch64GenSubtargetInfo {
bool isCyclone() const { return CPUString == "cyclone"; }
bool isCortexA57() const { return CPUString == "cortex-a57"; }
bool isCortexA53() const { return CPUString == "cortex-a53"; }
bool isExynosM1() const { return CPUString == "exynos-m1"; }

bool useAA() const override { return isCortexA53(); }

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8 changes: 8 additions & 0 deletions lib/Target/ARM/ARM.td
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Expand Up @@ -252,6 +252,8 @@ def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
"Swift ARM processors", []>;

def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
"Samsung Exynos-M1 processors", []>;

def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
"Cortex-R4 ARM processors", []>;
Expand Down Expand Up @@ -649,6 +651,12 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
FeatureCrypto,
FeatureZCZeroing]>;

def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
FeatureHWDiv,
FeatureHWDivARM,
FeatureT2XtPk,
FeatureCrypto,
FeatureCRC]>;

//===----------------------------------------------------------------------===//
// Register File Description
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2 changes: 1 addition & 1 deletion lib/Target/ARM/ARMSubtarget.h
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Expand Up @@ -44,7 +44,7 @@ class ARMSubtarget : public ARMGenSubtargetInfo {
enum ARMProcFamilyEnum {
Others, CortexA5, CortexA7, CortexA8, CortexA9, CortexA12, CortexA15,
CortexA17, CortexR4, CortexR4F, CortexR5, CortexR7, CortexA35, CortexA53,
CortexA57, CortexA72, Krait, Swift
CortexA57, CortexA72, Krait, Swift, ExynosM1
};
enum ARMProcClassEnum {
None, AClass, RClass, MClass
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1 change: 1 addition & 0 deletions test/CodeGen/AArch64/cpus.ll
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Expand Up @@ -6,6 +6,7 @@
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a53 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a57 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=cortex-a72 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m1 2>&1 | FileCheck %s
; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=invalidcpu 2>&1 | FileCheck %s --check-prefix=INVALID

; CHECK-NOT: {{.*}} is not a recognized processor for this target
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1 change: 1 addition & 0 deletions test/CodeGen/AArch64/remat.ll
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Expand Up @@ -2,6 +2,7 @@
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a57 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a53 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=cortex-a72 -o - %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnuabi -mcpu=exynos-m1 -o - %s | FileCheck %s

%X = type { i64, i64, i64 }
declare void @f(%X*)
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36 changes: 36 additions & 0 deletions test/CodeGen/ARM/build-attributes.ll
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Expand Up @@ -109,6 +109,9 @@
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A72-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a72 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=EXYNOS-M1
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=EXYNOS-M1-FAST
; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=exynos-m1 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=GENERIC-ARMV8_1-A-FAST
; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK
Expand Down Expand Up @@ -138,6 +141,9 @@
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a72 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=exynos-m1 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN

; ARMv7a
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
Expand Down Expand Up @@ -1238,6 +1244,36 @@
; CORTEX-A72-FAST-NOT: .eabi_attribute 22
; CORTEX-A72-FAST: .eabi_attribute 23, 1

; EXYNOS-M1: .cpu exynos-m1
; EXYNOS-M1: .eabi_attribute 6, 14
; EXYNOS-M1: .eabi_attribute 7, 65
; EXYNOS-M1: .eabi_attribute 8, 1
; EXYNOS-M1: .eabi_attribute 9, 2
; EXYNOS-M1: .fpu crypto-neon-fp-armv8
; EXYNOS-M1: .eabi_attribute 12, 3
; EXYNOS-M1-NOT: .eabi_attribute 19
;; We default to IEEE 754 compliance
; EXYNOS-M1: .eabi_attribute 20, 1
; EXYNOS-M1: .eabi_attribute 21, 1
; EXYNOS-M1-NOT: .eabi_attribute 22
; EXYNOS-M1: .eabi_attribute 23, 3
; EXYNOS-M1: .eabi_attribute 24, 1
; EXYNOS-M1: .eabi_attribute 25, 1
; EXYNOS-M1-NOT: .eabi_attribute 27
; EXYNOS-M1-NOT: .eabi_attribute 28
; EXYNOS-M1: .eabi_attribute 36, 1
; EXYNOS-M1: .eabi_attribute 38, 1
; EXYNOS-M1: .eabi_attribute 42, 1
; EXYNOS-M1-NOT: .eabi_attribute 44
; EXYNOS-M15: .eabi_attribute 68, 3

; EXYNOS-M1-FAST-NOT: .eabi_attribute 19
;; The exynos-m1 has the ARMv8 FP unit, which always flushes preserving sign.
; EXYNOS-M1-FAST: .eabi_attribute 20, 2
; EXYNOS-M1-FAST-NOT: .eabi_attribute 21
; EXYNOS-M1-FAST-NOT: .eabi_attribute 22
; EXYNOS-M1-FAST: .eabi_attribute 23, 1

; GENERIC-FPU-VFPV3-FP16: .fpu vfpv3-fp16
; GENERIC-FPU-VFPV3-D16-FP16: .fpu vfpv3-d16-fp16
; GENERIC-FPU-VFPV3XD: .fpu vfpv3xd
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