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Commits on Apr 5, 2016

• [NVPTX] Handle ldg created from sign-/zero-extended load

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Commits on Apr 28, 2015

• [NVPTX] Handle addrspacecast constant expressions in aggregate initializers

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Commits on Mar 30, 2015

• [NVPTX] Associate a minimum PTX version for each SM architecture

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• [NVPTX] Add options for PTX 4.1/4.2 and SM 3.2/3.7/5.2/5.3

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Commits on Jan 26, 2015

• [NVPTX] Generate a more optimal sequence for select of i1

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• [NVPTX] Handle floating-point conversion patterns that are not explicitly ordered or unordered

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Commits on Nov 5, 2014

• [NVPTX] Add NVPTXLowerStructArgs pass

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Commits on Jul 23, 2014

• [NVPTX] Add some extra tests for mul.wide to test non-power-of-two source types

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• [NVPTX] Silence a GCC warning found by the buildbots

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• [NVPTX] mul.wide generation works for any smaller integer source types, not just the next smaller power of two

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• [NVPTX] Make sure we do not generate MULWIDE ISD nodes when optimizations are disabled

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Commits on Jul 17, 2014

• [NVPTX] Improve handling of FP fusion

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• [NVPTX] Add missing .v4 qualifier on vector store instruction

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• [NVPTX] Flag surface/texture query instructions with IsTexSurfQuery

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• [NVPTX] Add more surface/texture intrinsics, including CUDA unified texture fetch

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• [TABLEGEN] Do not crash on intrinsics with names longer than 40 characters

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Commits on Jul 16, 2014

• [NVPTX] Honor alignment on vector loads/stores

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• [NVPTX] Rename registers %fl -> %fd and %rl -> %rd

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Commits on Jun 27, 2014

• [NVPTX] Use GreatestCommonDivisor64 from MathExtras instead of using our own. Thanks Hal!

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• [NVPTX] Add reflect intrinsic (better than matching by function name)

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• [NVPTX] Handle all possible vector types in getSetCCResultType, not just the ones representable as MVTs

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• [NVPTX] Add 'b' asm constraint

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• [NVPTX] Simplify some argument lowering logic

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• [NVPTX] Do not process samplers in GenericToNVVM

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• [NVPTX] Error out if initializer is given for variable in an address space that does not support initialization

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• [NVPTX] Add support for .managed variables for UVM

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• [NVPTX] Emit .weak linkage for link_once, weak, available_externally, and common linkage

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• [NVPTX] Variables that start with llvm. or nvvm. are reserved and should not be emitted

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• [NVPTX] Fix handling of ldg/ldu intrinsics.

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• [NVPTX] Clean up argument lowering code and properly handle alignment for structs and vectors

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• [NVPTX] Add missing boolean vector contents flag

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• [NVPTX] Add support for [SHL,SRA,SRL]_PARTS

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• [NVPTX] Implement fma and imad contraction as target DAGCombiner patterns

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• [NVPTX] Add support for efficient rotate instructions on SM 3.2+

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• [NVPTX] Add missing isel patterns for 64-bit atomics

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