md: fix VDP behaviors in corner / undocumented cases #362
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Bits 10-15 in control port read (aka status register) are not fixed as found in some online docs, but they are actually an open bus that returns the instruction prefetched by m68k at that cycle.
Mode5 (SMS compatibility mode) is unsupported and mostly undocumented, but the vdpfifotesting ROM at least checks one know behavior: non-SMS registers can't be written.
VSRAM is actually made of 40 11-bit words, though the chip only accesses the first 10 bits. The top bit on each word is still readable and writable though, so they should be emulated. Also, reading at addresses >= 40 returns a copy of the first word, rather than 0.
Reading unmapped bits in CRAM and VSRAM returns a copy of the same bits in the top slot of the FIFO.
Using target 0xC, it is possible to do 8-bit reads from VRAM.
VRAM misaligned addresses were implemented with partial slot reads. This seems to be wrong, as proven by vdpfifotesting: once the slot is read, the whole word is invalidated.
This was referenced Feb 17, 2022
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This commit series fixes VDP behaviors in several corner (undocumented) cases, as verified by VDPFifoTesting. After this PR lands, 121 tests out of 122 pass. The last failing test is the infamous test #16 which relates to VDP FIFO timings; Ares already performs very well in that last test (only one word is wrong), but it is tricky to fix. I'll leave that for later.