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Merge tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/k…
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…ernel/git/khilman/linux-amlogic into next/late

Pull "Amlogic driver updates for v4.9, 2nd round" from Kevin Hilman:

- media: update IR support for newer SoCs
- firmware: add secure monitor driver
- net: new stmmac glue driver
- usb: udd DWC2 support for meson-gxbb
- clocks: expose more clock IDs for use by DT
- DT binding updates

* tag 'amlogic-drivers-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (21 commits)
  clk: gxbb: expose i2c clocks
  clk: gxbb: expose USB clocks
  clk: gxbb: expose spifc clock
  clk: gxbb: expose MPLL2 clock for use by DT
  Documentation: dt-bindings: Add documentation for the Meson USB2 PHYs
  usb: dwc2: add support for Meson8b and GXBB SoCs
  net: stmmac: update the module description of the dwmac-meson driver
  net: stmmac: add a glue driver for the Amlogic Meson 8b / GXBB DWMAC
  stmmac: introduce get_stmmac_bsp_priv() helper
  net: dt-bindings: Document the new Meson8b and GXBB DWMAC bindings
  clk: meson-gxbb: Export PWM related clocks for DT
  meson: clk: Add support for clock gates
  gxbb: clk: Adjust MESON_GATE macro to be shared with meson8b
  clk: meson: Copy meson8b CLKID defines to private header file
  meson: clk: Rename register names according to Amlogic datasheet
  meson: clk: Move register definitions to meson8b.h
  clk: meson: Rename meson8b-clkc.c to reflect gxbb naming convention
  nvmem: amlogic: Add Amlogic Meson EFUSE driver
  firmware: Amlogic: Add secure monitor driver
  media: rc: meson-ir: Add support for newer versions of the IR decoder
  ...
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@arndb
arndb committed Sep 19, 2016
2 parents bac6dd3 + dfdd7d4 commit 53570cb
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Showing 27 changed files with 1,397 additions and 148 deletions.
45 changes: 37 additions & 8 deletions Documentation/devicetree/bindings/net/meson-dwmac.txt
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Original file line number Diff line number Diff line change
@@ -1,18 +1,32 @@
* Amlogic Meson DWMAC Ethernet controller

The device inherits all the properties of the dwmac/stmmac devices
described in the file net/stmmac.txt with the following changes.
described in the file stmmac.txt in the current directory with the
following changes.

Required properties:
Required properties on all platforms:

- compatible: should be "amlogic,meson6-dwmac" along with "snps,dwmac"
and any applicable more detailed version number
described in net/stmmac.txt
- compatible: Depending on the platform this should be one of:
- "amlogic,meson6-dwmac"
- "amlogic,meson8b-dwmac"
- "amlogic,meson-gxbb-dwmac"
Additionally "snps,dwmac" and any applicable more
detailed version number described in net/stmmac.txt
should be used.

- reg: should contain a register range for the dwmac controller and
another one for the Amlogic specific configuration
- reg: The first register range should be the one of the DWMAC
controller. The second range is is for the Amlogic specific
configuration (for example the PRG_ETHERNET register range
on Meson8b and newer)

Example:
Required properties on Meson8b and newer:
- clock-names: Should contain the following:
- "stmmaceth" - see stmmac.txt
- "clkin0" - first parent clock of the internal mux
- "clkin1" - second parent clock of the internal mux


Example for Meson6:

ethmac: ethernet@c9410000 {
compatible = "amlogic,meson6-dwmac", "snps,dwmac";
Expand All @@ -23,3 +37,18 @@ Example:
clocks = <&clk81>;
clock-names = "stmmaceth";
}

Example for GXBB:
ethmac: ethernet@c9410000 {
compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
reg = <0x0 0xc9410000 0x0 0x10000>,
<0x0 0xc8834540 0x0 0x8>;
interrupts = <0 8 1>;
interrupt-names = "macirq";
clocks = <&clkc CLKID_ETH>,
<&clkc CLKID_FCLK_DIV2>,
<&clkc CLKID_MPLL2>;
clock-names = "stmmaceth", "clkin0", "clkin1";
phy-mode = "rgmii";
status = "disabled";
};
27 changes: 27 additions & 0 deletions Documentation/devicetree/bindings/phy/meson-usb2-phy.txt
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Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
* Amlogic USB2 PHY

Required properties:
- compatible: Depending on the platform this should be one of:
"amlogic,meson8b-usb2-phy"
"amlogic,meson-gxbb-usb2-phy"
- reg: The base address and length of the registers
- #phys-cells: should be 0 (see phy-bindings.txt in this directory)
- clocks: phandle and clock identifier for the phy clocks
- clock-names: "usb_general" and "usb"

Optional properties:
- resets: reference to the reset controller
- phy-supply: see phy-bindings.txt in this directory


Example:

usb0_phy: usb_phy@0 {
compatible = "amlogic,meson-gxbb-usb2-phy";
#phy-cells = <0>;
reg = <0x0 0x0 0x0 0x20>;
resets = <&reset RESET_USB_OTG>;
clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
clock-names = "usb_general", "usb";
phy-supply = <&usb_vbus>;
};
2 changes: 2 additions & 0 deletions Documentation/devicetree/bindings/usb/dwc2.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,8 @@ Required properties:
- "rockchip,rk3288-usb", "rockchip,rk3066-usb", "snps,dwc2": for rk3288 Soc;
- "lantiq,arx100-usb": The DWC2 USB controller instance in Lantiq ARX SoCs;
- "lantiq,xrx200-usb": The DWC2 USB controller instance in Lantiq XRX SoCs;
- "amlogic,meson8b-usb": The DWC2 USB controller instance in Amlogic Meson8b SoCs;
- "amlogic,meson-gxbb-usb": The DWC2 USB controller instance in Amlogic S905 SoCs;
- snps,dwc2: A generic DWC2 USB controller with default parameters.
- reg : Should contain 1 register range (address and length)
- interrupts : Should contain 1 interrupt
Expand Down
2 changes: 1 addition & 1 deletion drivers/clk/meson/Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -3,5 +3,5 @@
#

obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o
2 changes: 1 addition & 1 deletion drivers/clk/meson/clkc.h
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Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ struct meson_clk_mpll {
};

#define MESON_GATE(_name, _reg, _bit) \
struct clk_gate gxbb_##_name = { \
struct clk_gate _name = { \
.reg = (void __iomem *) _reg, \
.bit_idx = (_bit), \
.lock = &clk_lock, \
Expand Down
171 changes: 90 additions & 81 deletions drivers/clk/meson/gxbb.c
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Original file line number Diff line number Diff line change
Expand Up @@ -565,90 +565,93 @@ static struct clk_gate gxbb_clk81 = {
};

/* Everything Else (EE) domain gates */
static MESON_GATE(ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(dos, HHI_GCLK_MPEG0, 1);
static MESON_GATE(isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(sar_adc, HHI_GCLK_MPEG0, 10);
static MESON_GATE(smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(sdhc, HHI_GCLK_MPEG0, 14);
static MESON_GATE(stream, HHI_GCLK_MPEG0, 15);
static MESON_GATE(async_fifo, HHI_GCLK_MPEG0, 16);
static MESON_GATE(sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(spi, HHI_GCLK_MPEG0, 30);

static MESON_GATE(i2s_spdif, HHI_GCLK_MPEG1, 2);
static MESON_GATE(eth, HHI_GCLK_MPEG1, 3);
static MESON_GATE(demux, HHI_GCLK_MPEG1, 4);
static MESON_GATE(aiu_glue, HHI_GCLK_MPEG1, 6);
static MESON_GATE(iec958, HHI_GCLK_MPEG1, 7);
static MESON_GATE(i2s_out, HHI_GCLK_MPEG1, 8);
static MESON_GATE(amclk, HHI_GCLK_MPEG1, 9);
static MESON_GATE(aififo2, HHI_GCLK_MPEG1, 10);
static MESON_GATE(mixer, HHI_GCLK_MPEG1, 11);
static MESON_GATE(mixer_iface, HHI_GCLK_MPEG1, 12);
static MESON_GATE(adc, HHI_GCLK_MPEG1, 13);
static MESON_GATE(blkmv, HHI_GCLK_MPEG1, 14);
static MESON_GATE(aiu, HHI_GCLK_MPEG1, 15);
static MESON_GATE(uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(nand, HHI_GCLK_MPEG1, 24);
static MESON_GATE(dos_parser, HHI_GCLK_MPEG1, 25);
static MESON_GATE(usb, HHI_GCLK_MPEG1, 26);
static MESON_GATE(vdin1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(boot_rom, HHI_GCLK_MPEG1, 31);

static MESON_GATE(ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static MESON_GATE(hdmi_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static MESON_GATE(usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(sana, HHI_GCLK_MPEG2, 22);
static MESON_GATE(vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(clk81_a53, HHI_GCLK_MPEG2, 29);

static MESON_GATE(vclk2_venci0, HHI_GCLK_OTHER, 1);
static MESON_GATE(vclk2_venci1, HHI_GCLK_OTHER, 2);
static MESON_GATE(vclk2_vencp0, HHI_GCLK_OTHER, 3);
static MESON_GATE(vclk2_vencp1, HHI_GCLK_OTHER, 4);
static MESON_GATE(gclk_venci_int0, HHI_GCLK_OTHER, 8);
static MESON_GATE(gclk_vencp_int, HHI_GCLK_OTHER, 9);
static MESON_GATE(dac_clk, HHI_GCLK_OTHER, 10);
static MESON_GATE(aoclk_gate, HHI_GCLK_OTHER, 14);
static MESON_GATE(iec958_gate, HHI_GCLK_OTHER, 16);
static MESON_GATE(enc480p, HHI_GCLK_OTHER, 20);
static MESON_GATE(rng1, HHI_GCLK_OTHER, 21);
static MESON_GATE(gclk_venci_int1, HHI_GCLK_OTHER, 22);
static MESON_GATE(vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static MESON_GATE(vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(vclk_other, HHI_GCLK_OTHER, 26);
static MESON_GATE(edp, HHI_GCLK_OTHER, 31);
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
static MESON_GATE(gxbb_isa, HHI_GCLK_MPEG0, 5);
static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6);
static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7);
static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8);
static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9);
static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10);
static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11);
static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12);
static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13);
static MESON_GATE(gxbb_sdhc, HHI_GCLK_MPEG0, 14);
static MESON_GATE(gxbb_stream, HHI_GCLK_MPEG0, 15);
static MESON_GATE(gxbb_async_fifo, HHI_GCLK_MPEG0, 16);
static MESON_GATE(gxbb_sdio, HHI_GCLK_MPEG0, 17);
static MESON_GATE(gxbb_abuf, HHI_GCLK_MPEG0, 18);
static MESON_GATE(gxbb_hiu_iface, HHI_GCLK_MPEG0, 19);
static MESON_GATE(gxbb_assist_misc, HHI_GCLK_MPEG0, 23);
static MESON_GATE(gxbb_emmc_a, HHI_GCLK_MPEG0, 24);
static MESON_GATE(gxbb_emmc_b, HHI_GCLK_MPEG0, 25);
static MESON_GATE(gxbb_emmc_c, HHI_GCLK_MPEG0, 26);
static MESON_GATE(gxbb_spi, HHI_GCLK_MPEG0, 30);

static MESON_GATE(gxbb_i2s_spdif, HHI_GCLK_MPEG1, 2);
static MESON_GATE(gxbb_eth, HHI_GCLK_MPEG1, 3);
static MESON_GATE(gxbb_demux, HHI_GCLK_MPEG1, 4);
static MESON_GATE(gxbb_aiu_glue, HHI_GCLK_MPEG1, 6);
static MESON_GATE(gxbb_iec958, HHI_GCLK_MPEG1, 7);
static MESON_GATE(gxbb_i2s_out, HHI_GCLK_MPEG1, 8);
static MESON_GATE(gxbb_amclk, HHI_GCLK_MPEG1, 9);
static MESON_GATE(gxbb_aififo2, HHI_GCLK_MPEG1, 10);
static MESON_GATE(gxbb_mixer, HHI_GCLK_MPEG1, 11);
static MESON_GATE(gxbb_mixer_iface, HHI_GCLK_MPEG1, 12);
static MESON_GATE(gxbb_adc, HHI_GCLK_MPEG1, 13);
static MESON_GATE(gxbb_blkmv, HHI_GCLK_MPEG1, 14);
static MESON_GATE(gxbb_aiu, HHI_GCLK_MPEG1, 15);
static MESON_GATE(gxbb_uart1, HHI_GCLK_MPEG1, 16);
static MESON_GATE(gxbb_g2d, HHI_GCLK_MPEG1, 20);
static MESON_GATE(gxbb_usb0, HHI_GCLK_MPEG1, 21);
static MESON_GATE(gxbb_usb1, HHI_GCLK_MPEG1, 22);
static MESON_GATE(gxbb_reset, HHI_GCLK_MPEG1, 23);
static MESON_GATE(gxbb_nand, HHI_GCLK_MPEG1, 24);
static MESON_GATE(gxbb_dos_parser, HHI_GCLK_MPEG1, 25);
static MESON_GATE(gxbb_usb, HHI_GCLK_MPEG1, 26);
static MESON_GATE(gxbb_vdin1, HHI_GCLK_MPEG1, 28);
static MESON_GATE(gxbb_ahb_arb0, HHI_GCLK_MPEG1, 29);
static MESON_GATE(gxbb_efuse, HHI_GCLK_MPEG1, 30);
static MESON_GATE(gxbb_boot_rom, HHI_GCLK_MPEG1, 31);

static MESON_GATE(gxbb_ahb_data_bus, HHI_GCLK_MPEG2, 1);
static MESON_GATE(gxbb_ahb_ctrl_bus, HHI_GCLK_MPEG2, 2);
static MESON_GATE(gxbb_hdmi_intr_sync, HHI_GCLK_MPEG2, 3);
static MESON_GATE(gxbb_hdmi_pclk, HHI_GCLK_MPEG2, 4);
static MESON_GATE(gxbb_usb1_ddr_bridge, HHI_GCLK_MPEG2, 8);
static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, 9);
static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11);
static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12);
static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15);
static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22);
static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25);
static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26);
static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);

static MESON_GATE(gxbb_vclk2_venci0, HHI_GCLK_OTHER, 1);
static MESON_GATE(gxbb_vclk2_venci1, HHI_GCLK_OTHER, 2);
static MESON_GATE(gxbb_vclk2_vencp0, HHI_GCLK_OTHER, 3);
static MESON_GATE(gxbb_vclk2_vencp1, HHI_GCLK_OTHER, 4);
static MESON_GATE(gxbb_gclk_venci_int0, HHI_GCLK_OTHER, 8);
static MESON_GATE(gxbb_gclk_vencp_int, HHI_GCLK_OTHER, 9);
static MESON_GATE(gxbb_dac_clk, HHI_GCLK_OTHER, 10);
static MESON_GATE(gxbb_aoclk_gate, HHI_GCLK_OTHER, 14);
static MESON_GATE(gxbb_iec958_gate, HHI_GCLK_OTHER, 16);
static MESON_GATE(gxbb_enc480p, HHI_GCLK_OTHER, 20);
static MESON_GATE(gxbb_rng1, HHI_GCLK_OTHER, 21);
static MESON_GATE(gxbb_gclk_venci_int1, HHI_GCLK_OTHER, 22);
static MESON_GATE(gxbb_vclk2_venclmcc, HHI_GCLK_OTHER, 24);
static MESON_GATE(gxbb_vclk2_vencl, HHI_GCLK_OTHER, 25);
static MESON_GATE(gxbb_vclk_other, HHI_GCLK_OTHER, 26);
static MESON_GATE(gxbb_edp, HHI_GCLK_OTHER, 31);

/* Always On (AO) domain gates */

static MESON_GATE(ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(ao_i2c, HHI_GCLK_AO, 4);
static MESON_GATE(gxbb_ao_media_cpu, HHI_GCLK_AO, 0);
static MESON_GATE(gxbb_ao_ahb_sram, HHI_GCLK_AO, 1);
static MESON_GATE(gxbb_ao_ahb_bus, HHI_GCLK_AO, 2);
static MESON_GATE(gxbb_ao_iface, HHI_GCLK_AO, 3);
static MESON_GATE(gxbb_ao_i2c, HHI_GCLK_AO, 4);

/* Array of all clocks provided by this provider */

Expand Down Expand Up @@ -748,6 +751,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_AO_AHB_BUS] = &gxbb_ao_ahb_bus.hw,
[CLKID_AO_IFACE] = &gxbb_ao_iface.hw,
[CLKID_AO_I2C] = &gxbb_ao_i2c.hw,
[CLKID_SD_EMMC_A] = &gxbb_emmc_a.hw,
[CLKID_SD_EMMC_B] = &gxbb_emmc_b.hw,
[CLKID_SD_EMMC_C] = &gxbb_emmc_c.hw,
},
.num = NR_CLKS,
};
Expand Down Expand Up @@ -847,6 +853,9 @@ static struct clk_gate *gxbb_clk_gates[] = {
&gxbb_ao_ahb_bus,
&gxbb_ao_iface,
&gxbb_ao_i2c,
&gxbb_emmc_a,
&gxbb_emmc_b,
&gxbb_emmc_c,
};

static int gxbb_clkc_probe(struct platform_device *pdev)
Expand Down
31 changes: 17 additions & 14 deletions drivers/clk/meson/gxbb.h
View file
Original file line number Diff line number Diff line change
Expand Up @@ -170,11 +170,11 @@
*/
#define CLKID_SYS_PLL 0
/* CLKID_CPUCLK */
#define CLKID_HDMI_PLL 2
/* CLKID_HDMI_PLL */
#define CLKID_FIXED_PLL 3
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
/* CLKID_FCLK_DIV2 */
/* CLKID_FCLK_DIV3 */
/* CLKID_FCLK_DIV4 */
#define CLKID_FCLK_DIV5 7
#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
Expand All @@ -183,14 +183,14 @@
/* CLKID_CLK81 */
#define CLKID_MPLL0 13
#define CLKID_MPLL1 14
#define CLKID_MPLL2 15
/* CLKID_MPLL2 */
#define CLKID_DDR 16
#define CLKID_DOS 17
#define CLKID_ISA 18
#define CLKID_PL301 19
#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
#define CLKID_I2C 22
/* CLKID_I2C */
#define CLKID_SAR_ADC 23
#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
Expand All @@ -202,7 +202,7 @@
#define CLKID_ABUF 31
#define CLKID_HIU_IFACE 32
#define CLKID_ASSIST_MISC 33
#define CLKID_SPI 34
/* CLKID_SPI */
#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
#define CLKID_DEMUX 37
Expand All @@ -218,12 +218,12 @@
#define CLKID_AIU 47
#define CLKID_UART1 48
#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
/* CLKID_USB0 */
/* CLKID_USB1 */
#define CLKID_RESET 52
#define CLKID_NAND 53
#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
/* CLKID_USB */
#define CLKID_VDIN1 56
#define CLKID_AHB_ARB0 57
#define CLKID_EFUSE 58
Expand All @@ -232,8 +232,8 @@
#define CLKID_AHB_CTRL_BUS 61
#define CLKID_HDMI_INTR_SYNC 62
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
/* CLKID_USB1_DDR_BRIDGE */
/* CLKID_USB0_DDR_BRIDGE */
#define CLKID_MMC_PCLK 66
#define CLKID_DVIN 67
#define CLKID_UART2 68
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#define CLKID_AO_AHB_SRAM 90
#define CLKID_AO_AHB_BUS 91
#define CLKID_AO_IFACE 92
#define CLKID_AO_I2C 93
/* CLKID_AO_I2C */
/* CLKID_SD_EMMC_A */
/* CLKID_SD_EMMC_B */
/* CLKID_SD_EMMC_C */

#define NR_CLKS 94
#define NR_CLKS 97

/* include the CLKIDs that have been made part of the stable DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
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