Merge tag 'riscv-for-linus-5.8-rc6' of git://git.kernel.org/pub/scm/l…

…inux/kernel/git/riscv/linux into master

Pull RISC-V fixes from Palmer Dabbelt:
 "Two fixes:

   - 16KiB kernel stacks on rv64, which fixes a lot of crashes.

   - Rolling an mmiowb() into the scheduler, which when combined with
     Will's fix to the mmiowb()-on-spinlock should fix the PREEMPT
     issues we've been seeing"

* tag 'riscv-for-linus-5.8-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux:
  RISC-V: Upgrade smp_mb__after_spinlock() to iorw,iorw
  riscv: use 16KB kernel stack on 64-bit

arch/riscv/include/asm/barrier.h

@@ -58,8 +58,16 @@ do {									\
  * The AQ/RL pair provides a RCpc critical section, but there's not really any
  * way we can take advantage of that here because the ordering is only enforced
  * on that one lock.  Thus, we're just doing a full fence.
+ *
+ * Since we allow writeX to be called from preemptive regions we need at least
+ * an "o" in the predecessor set to ensure device writes are visible before the
+ * task is marked as available for scheduling on a new hart.  While I don't see
+ * any concrete reason we need a full IO fence, it seems safer to just upgrade
+ * this in order to avoid any IO crossing a scheduling boundary.  In both
+ * instances the scheduler pairs this with an mb(), so nothing is necessary on
+ * the new hart.
  */
-#define smp_mb__after_spinlock()	RISCV_FENCE(rw,rw)
+#define smp_mb__after_spinlock()	RISCV_FENCE(iorw,iorw)
 
 #include <asm-generic/barrier.h>
 

arch/riscv/include/asm/thread_info.h

@@ -12,7 +12,11 @@
 #include <linux/const.h>
 
 /* thread information allocation */
+#ifdef CONFIG_64BIT
+#define THREAD_SIZE_ORDER	(2)
+#else
 #define THREAD_SIZE_ORDER	(1)
+#endif
 #define THREAD_SIZE		(PAGE_SIZE << THREAD_SIZE_ORDER)
 
 #ifndef __ASSEMBLY__