dt-bindings: riscv: Update DT binding docs to support SiFive FU740 SoC

Add new compatible strings in cpus.yaml to support the E71 and U74 CPU cores ("harts") that are present on FU740-C000 SoC. Signed-off-by: Yash Shah <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
ashr · Jan 8, 2021 · 75e6d72 · 75e6d72
1 parent 507308b
commit 75e6d72
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -28,11 +28,17 @@ properties:
       - items:
           - enum:
               - sifive,rocket0
+              - sifive,bullet0
               - sifive,e5
+              - sifive,e7
               - sifive,e51
+              - sifive,e71
               - sifive,u54-mc
+              - sifive,u74-mc
               - sifive,u54
+              - sifive,u74
               - sifive,u5
+              - sifive,u7
           - const: riscv
       - const: riscv    # Simulator only
     description: