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Revert "AVX512: Implemented encoding and intrinsics for vextracti64x4…
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… ,vextracti64x2, vextracti32x8, vextracti32x4, vextractf64x4, vextractf64x2, vextractf32x8, vextractf32x4 Added tests for intrinsics and encoding."

This reverts commit r247149, as it was breaking numerous buildbots of varied architectures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@247177 91177308-0d34-0410-b5e6-96231b3b80d8
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@rengolin
rengolin committed Sep 9, 2015
1 parent 97878fc commit 792b67e
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Showing 12 changed files with 89 additions and 1,145 deletions.
48 changes: 8 additions & 40 deletions include/llvm/IR/IntrinsicsX86.td
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Original file line number Diff line number Diff line change
Expand Up @@ -2233,52 +2233,20 @@ let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
let TargetPrefix = "x86" in { // All intrinsics start with "llvm.x86.".
def int_x86_avx512_mask_vextractf32x4_512 :
GCCBuiltin<"__builtin_ia32_extractf32x4_mask">,
Intrinsic<[llvm_v4f32_ty], [llvm_v16f32_ty, llvm_i32_ty,
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4f32_ty], [llvm_v16f32_ty, llvm_i8_ty,
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti32x4_512 :
GCCBuiltin<"__builtin_ia32_extracti32x4_mask">,
Intrinsic<[llvm_v4i32_ty], [llvm_v16i32_ty, llvm_i32_ty,
llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextractf32x4_256 :
GCCBuiltin<"__builtin_ia32_extractf32x4_256_mask">,
Intrinsic<[llvm_v4f32_ty], [llvm_v8f32_ty, llvm_i32_ty,
llvm_v4f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti32x4_256 :
GCCBuiltin<"__builtin_ia32_extracti32x4_256_mask">,
Intrinsic<[llvm_v4i32_ty], [llvm_v8i32_ty, llvm_i32_ty,
llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextractf64x2_256 :
GCCBuiltin<"__builtin_ia32_extractf64x2_256_mask">,
Intrinsic<[llvm_v2f64_ty], [llvm_v4f64_ty, llvm_i32_ty,
llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti64x2_256 :
GCCBuiltin<"__builtin_ia32_extracti64x2_256_mask">,
Intrinsic<[llvm_v2i64_ty], [llvm_v4i64_ty, llvm_i32_ty,
llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextractf64x2_512 :
GCCBuiltin<"__builtin_ia32_extractf64x2_512_mask">,
Intrinsic<[llvm_v2f64_ty], [llvm_v8f64_ty, llvm_i32_ty,
llvm_v2f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti64x2_512 :
GCCBuiltin<"__builtin_ia32_extracti64x2_512_mask">,
Intrinsic<[llvm_v2i64_ty], [llvm_v8i64_ty, llvm_i32_ty,
llvm_v2i64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextractf32x8_512 :
GCCBuiltin<"__builtin_ia32_extractf32x8_mask">,
Intrinsic<[llvm_v8f32_ty], [llvm_v16f32_ty, llvm_i32_ty,
llvm_v8f32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti32x8_512 :
GCCBuiltin<"__builtin_ia32_extracti32x8_mask">,
Intrinsic<[llvm_v8i32_ty],[llvm_v16i32_ty, llvm_i32_ty,
llvm_v8i32_ty, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4i32_ty], [llvm_v16i32_ty, llvm_i8_ty,
llvm_v4i32_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextractf64x4_512 :
GCCBuiltin<"__builtin_ia32_extractf64x4_mask">,
Intrinsic<[llvm_v4f64_ty], [llvm_v8f64_ty, llvm_i32_ty,
llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4f64_ty], [llvm_v8f64_ty, llvm_i8_ty,
llvm_v4f64_ty, llvm_i8_ty], [IntrNoMem]>;
def int_x86_avx512_mask_vextracti64x4_512 :
GCCBuiltin<"__builtin_ia32_extracti64x4_mask">,
Intrinsic<[llvm_v4i64_ty], [llvm_v8i64_ty, llvm_i32_ty,
llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
Intrinsic<[llvm_v4i64_ty], [llvm_v8i64_ty, llvm_i8_ty,
llvm_v4i64_ty, llvm_i8_ty], [IntrNoMem]>;
}

// Conditional load ops
Expand Down
161 changes: 52 additions & 109 deletions lib/Target/X86/X86InstrAVX512.td
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Original file line number Diff line number Diff line change
Expand Up @@ -566,142 +566,85 @@ def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
// AVX-512 VECTOR EXTRACT
//---

multiclass vextract_for_size_first_position_lowering<X86VectorVTInfo From,
X86VectorVTInfo To> {
// A subvector extract from the first vector position is
// a subregister copy that needs no instruction.
def NAME # To.NumElts:
Pat<(To.VT (extract_subvector (From.VT From.RC:$src),(iPTR 0))),
(To.VT (EXTRACT_SUBREG (From.VT From.RC:$src), To.SubRegIdx))>;
}

multiclass vextract_for_size<int Opcode,
X86VectorVTInfo From, X86VectorVTInfo To,
PatFrag vextract_extract> :
vextract_for_size_first_position_lowering<From, To> {

X86VectorVTInfo From, X86VectorVTInfo To,
X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
PatFrag vextract_extract,
SDNodeXForm EXTRACT_get_vextract_imm> {
let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
// use AVX512_maskable_in_asm (AVX512_maskable can't be used due to
// vextract_extract), we interesting only in patterns without mask,
// intrinsics pattern match generated bellow.
defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
(ins From.RC:$src1, i32u8imm:$idx),
"vextract" # To.EltTypeName # "x" # To.NumElts,
(ins VR512:$src1, u8imm:$idx),
"vextract" # To.EltTypeName # "x4",
"$idx, $src1", "$src1, $idx",
[(set To.RC:$dst, (vextract_extract:$idx (From.VT From.RC:$src1),
[(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
(iPTR imm)))]>,
AVX512AIi8Base, EVEX;
let mayStore = 1 in {
def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, From.RC:$src1, i32u8imm:$src2),
"vextract" # To.EltTypeName # "x" # To.NumElts #
"\t{$src2, $src1, $dst|$dst, $src1, $src2}",
[]>, EVEX;

def rmk : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, To.KRCWM:$mask,
From.RC:$src1, i32u8imm:$src2),
"vextract" # To.EltTypeName # "x" # To.NumElts #
"\t{$src2, $src1, $dst {${mask}}|"
"$dst {${mask}}, $src1, $src2}",
[]>, EVEX_K, EVEX;
}//mayStore = 1
AVX512AIi8Base, EVEX, EVEX_V512;
let mayStore = 1 in
def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
(ins To.MemOp:$dst, VR512:$src1, u8imm:$src2),
"vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
"$dst, $src1, $src2}",
[]>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
}

// Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
// vextracti32x4
def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
(AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
VR512:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;

// A 128/256-bit subvector extract from the first 512-bit vector position is
// a subregister copy that needs no instruction.
def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
(To.VT
(EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;

// And for the alternative types.
def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
(AltTo.VT
(EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;

// Intrinsic call with masking.
def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
"x" # To.NumElts # "_" # From.Size)
From.RC:$src1, (iPTR imm:$idx), To.RC:$src0, To.MRC:$mask),
(!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
From.ZSuffix # "rrk")
To.RC:$src0,
(COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
From.RC:$src1, imm:$idx)>;
"x4_512")
VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
(!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
(v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
VR512:$src1, imm:$idx)>;

// Intrinsic call with zero-masking.
def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
"x" # To.NumElts # "_" # From.Size)
From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, To.MRC:$mask),
(!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
From.ZSuffix # "rrkz")
(COPY_TO_REGCLASS To.MRC:$mask, To.KRCWM),
From.RC:$src1, imm:$idx)>;
"x4_512")
VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
(!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
(v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
VR512:$src1, imm:$idx)>;

// Intrinsic call without masking.
def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
"x" # To.NumElts # "_" # From.Size)
From.RC:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
(!cast<Instruction>(NAME # To.EltSize # "x" # To.NumElts #
From.ZSuffix # "rr")
From.RC:$src1, imm:$idx)>;
}

// This multiclass generates patterns for matching vextract with common types
// (X86VectorVTInfo From , X86VectorVTInfo To) and alternative types
// (X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo)
multiclass vextract_for_size_all<int Opcode,
X86VectorVTInfo From, X86VectorVTInfo To,
X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
PatFrag vextract_extract,
SDNodeXForm EXTRACT_get_vextract_imm> :
vextract_for_size<Opcode, From, To, vextract_extract>,
vextract_for_size_first_position_lowering<AltFrom, AltTo> {

// Codegen pattern with the alternative types.
// Only add this if operation not supported natively via AVX512DQ
let Predicates = [NoDQI] in
def : Pat<(vextract_extract:$ext (AltFrom.VT AltFrom.RC:$src1), (iPTR imm)),
(AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x" #
To.NumElts # From.ZSuffix # "rr")
AltFrom.RC:$src1,
(EXTRACT_get_vextract_imm To.RC:$ext)))>;
"x4_512")
VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
(!cast<Instruction>(NAME # To.EltSize # "x4rr")
VR512:$src1, imm:$idx)>;
}

multiclass vextract_for_type<ValueType EltVT32, int Opcode128,
ValueType EltVT64, int Opcode256> {
defm NAME # "32x4Z" : vextract_for_size_all<Opcode128,
multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
ValueType EltVT64, int Opcode64> {
defm NAME # "32x4" : vextract_for_size<Opcode32,
X86VectorVTInfo<16, EltVT32, VR512>,
X86VectorVTInfo< 4, EltVT32, VR128X>,
X86VectorVTInfo< 8, EltVT64, VR512>,
X86VectorVTInfo< 2, EltVT64, VR128X>,
vextract128_extract,
EXTRACT_get_vextract128_imm>,
EVEX_V512, EVEX_CD8<32, CD8VT4>;
defm NAME # "64x4Z" : vextract_for_size_all<Opcode256,
EXTRACT_get_vextract128_imm>;
defm NAME # "64x4" : vextract_for_size<Opcode64,
X86VectorVTInfo< 8, EltVT64, VR512>,
X86VectorVTInfo< 4, EltVT64, VR256X>,
X86VectorVTInfo<16, EltVT32, VR512>,
X86VectorVTInfo< 8, EltVT32, VR256>,
vextract256_extract,
EXTRACT_get_vextract256_imm>,
VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT4>;
let Predicates = [HasVLX] in
defm NAME # "32x4Z256" : vextract_for_size_all<Opcode128,
X86VectorVTInfo< 8, EltVT32, VR256X>,
X86VectorVTInfo< 4, EltVT32, VR128X>,
X86VectorVTInfo< 4, EltVT64, VR256X>,
X86VectorVTInfo< 2, EltVT64, VR128X>,
vextract128_extract,
EXTRACT_get_vextract128_imm>,
EVEX_V256, EVEX_CD8<32, CD8VT4>;
let Predicates = [HasVLX, HasDQI] in
defm NAME # "64x2Z256" : vextract_for_size<Opcode128,
X86VectorVTInfo< 4, EltVT64, VR256X>,
X86VectorVTInfo< 2, EltVT64, VR128X>,
vextract128_extract>,
VEX_W, EVEX_V256, EVEX_CD8<64, CD8VT2>;
let Predicates = [HasDQI] in {
defm NAME # "64x2Z" : vextract_for_size<Opcode128,
X86VectorVTInfo< 8, EltVT64, VR512>,
X86VectorVTInfo< 2, EltVT64, VR128X>,
vextract128_extract>,
VEX_W, EVEX_V512, EVEX_CD8<64, CD8VT2>;
defm NAME # "32x8Z" : vextract_for_size<Opcode256,
X86VectorVTInfo<16, EltVT32, VR512>,
X86VectorVTInfo< 8, EltVT32, VR256X>,
vextract256_extract>,
EVEX_V512, EVEX_CD8<32, CD8VT8>;
}
EXTRACT_get_vextract256_imm>, VEX_W;
}

defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
Expand Down
18 changes: 8 additions & 10 deletions test/CodeGen/X86/avx512-cvt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,14 +52,14 @@ define <4 x i64> @f32tosl(<4 x float> %a) {
}

; CHECK-LABEL: sltof432
; CHECK: vcvtqq2ps
; CHECK: vcvtqq2ps
define <4 x float> @sltof432(<4 x i64> %a) {
%b = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %b
}

; CHECK-LABEL: ultof432
; CHECK: vcvtuqq2ps
; CHECK: vcvtuqq2ps
define <4 x float> @ultof432(<4 x i64> %a) {
%b = uitofp <4 x i64> %a to <4 x float>
ret <4 x float> %b
Expand Down Expand Up @@ -279,14 +279,12 @@ define i32 @float_to_int(float %x) {
ret i32 %res
}

; CHECK-LABEL: uitof64
; CHECK: vcvtudq2pd
; CHECK: vextracti64x4
; CHECK: vcvtudq2pd
; CHECK: ret
define <16 x double> @uitof64(<16 x i32> %a) nounwind {
; CHECK-LABEL: uitof64:
; CHECK: ## BB#0:
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm2
; CHECK-NEXT: vextracti32x8 $1, %zmm0, %ymm0
; CHECK-NEXT: vcvtudq2pd %ymm0, %zmm1
; CHECK-NEXT: vmovaps %zmm2, %zmm0
; CHECK-NEXT: retq
%b = uitofp <16 x i32> %a to <16 x double>
ret <16 x double> %b
}
Expand Down Expand Up @@ -409,7 +407,7 @@ define <8 x double> @sitofp_8i1_double(<8 x double> %a) {
}

; CHECK-LABEL: @uitofp_16i8
; CHECK: vpmovzxbd
; CHECK: vpmovzxbd
; CHECK: vcvtudq2ps
define <16 x float> @uitofp_16i8(<16 x i8>%a) {
%b = uitofp <16 x i8> %a to <16 x float>
Expand Down
46 changes: 13 additions & 33 deletions test/CodeGen/X86/avx512-insert-extract.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,24 +12,14 @@ define <16 x float> @test1(<16 x float> %x, float* %br, float %y) nounwind {
ret <16 x float> %rrr3
}

;CHECK-LABEL: test2:
;KNL: vinsertf32x4 $0
;SKX: vinsertf64x2 $0
;CHECK: vextractf32x4 $3
;KNL: vinsertf32x4 $3
;SKX: vinsertf64x2 $3
;CHECK: ret
define <8 x double> @test2(<8 x double> %x, double* %br, double %y) nounwind {
; KNL-LABEL: test2:
; KNL: ## BB#0:
; KNL-NEXT: vmovhpd (%rdi), %xmm0, %xmm2
; KNL-NEXT: vinsertf32x4 $0, %xmm2, %zmm0, %zmm0
; KNL-NEXT: vextractf32x4 $3, %zmm0, %xmm2
; KNL-NEXT: vmovsd %xmm1, %xmm2, %xmm1
; KNL-NEXT: vinsertf32x4 $3, %xmm1, %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test2:
; SKX: ## BB#0:
; SKX-NEXT: vmovhpd (%rdi), %xmm0, %xmm2
; SKX-NEXT: vinsertf64x2 $0, %xmm2, %zmm0, %zmm0
; SKX-NEXT: vextractf64x2 $3, %zmm0, %xmm2
; SKX-NEXT: vmovsd %xmm1, %xmm2, %xmm1
; SKX-NEXT: vinsertf64x2 $3, %xmm1, %zmm0, %zmm0
; SKX-NEXT: retq
%rrr = load double, double* %br
%rrr2 = insertelement <8 x double> %x, double %rrr, i32 1
%rrr3 = insertelement <8 x double> %rrr2, double %y, i32 6
Expand All @@ -46,22 +36,12 @@ define <16 x float> @test3(<16 x float> %x) nounwind {
ret <16 x float> %rrr2
}

;CHECK-LABEL: test4:
;CHECK: vextracti32x4 $2
;KNL: vinserti32x4 $0
;SKX: vinserti64x2 $0
;CHECK: ret
define <8 x i64> @test4(<8 x i64> %x) nounwind {
; KNL-LABEL: test4:
; KNL: ## BB#0:
; KNL-NEXT: vextracti32x4 $2, %zmm0, %xmm1
; KNL-NEXT: vmovq %xmm1, %rax
; KNL-NEXT: vpinsrq $1, %rax, %xmm0, %xmm1
; KNL-NEXT: vinserti32x4 $0, %xmm1, %zmm0, %zmm0
; KNL-NEXT: retq
;
; SKX-LABEL: test4:
; SKX: ## BB#0:
; SKX-NEXT: vextracti64x2 $2, %zmm0, %xmm1
; SKX-NEXT: vmovq %xmm1, %rax
; SKX-NEXT: vpinsrq $1, %rax, %xmm0, %xmm1
; SKX-NEXT: vinserti64x2 $0, %xmm1, %zmm0, %zmm0
; SKX-NEXT: retq
%eee = extractelement <8 x i64> %x, i32 4
%rrr2 = insertelement <8 x i64> %x, i64 %eee, i32 1
ret <8 x i64> %rrr2
Expand Down Expand Up @@ -162,7 +142,7 @@ define i64 @test12(<16 x i64>%a, <16 x i64>%b, i64 %a1, i64 %b1) {
;CHECK: andl $1, %eax
;CHECK: kmovw %eax, %k0
;CHECK: movw $-4
;CHECK: korw
;CHECK: korw
define i16 @test13(i32 %a, i32 %b) {
%cmp_res = icmp ult i32 %a, %b
%maskv = insertelement <16 x i1> <i1 true, i1 false, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, i1 %cmp_res, i32 0
Expand Down
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