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Commits on Mar 9, 2016

• [PPC] backend changes to generate xvabs[s,d]p and xvnabs[s,d]p instructions

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Commits on Mar 8, 2016

• [Power9] Implement new vsx instructions: load, store instructions for vector and scalar

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Commits on Mar 1, 2016

• [Power9] Implement new vector compare, extract, insert instructions

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• New file to track implementation status of new POWER9 instructions

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Commits on Feb 26, 2016

• [PPC] Legalize FNEG on PPC when possible

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• Power9] Implement new vsx instructions: compare and conversion

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Commits on Dec 7, 2015

• [PPC64] Convert bool literals to i32

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Commits on Nov 30, 2015

• Enable shrink wrapping for PPC64

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Commits on Nov 16, 2015

• Find available scratch register to use in function prologue and epilogue as part of shrink wrapping.

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Commits on Sep 10, 2015

• Enable the shrink wrapping optimization for PPC64.

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Commits on Aug 31, 2015

• Rework of the new interface for shrink wrapping

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Commits on Aug 14, 2015

• Reverting patch r244235.

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Commits on Aug 6, 2015

• Fix possible infinite loop in shrink wrapping when searching for save/restore

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• This patch changes the interface to enable the shrink wrapping optimization.

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Commits on Jun 25, 2015

• [PPC] Implement vmrgew and vmrgow instructions

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Commits on Jun 16, 2015

• Properly handle the mftb instruction.

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Commits on May 25, 2015

• This patch adds support for the vector quadword add/sub instructions introduced

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Commits on May 5, 2015

• This patch adds ABI support for v1i128 data type.

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Commits on Apr 17, 2015

• Add support for v1i128 type.

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• Add the i128 builtin type to LLVM.

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Commits on Mar 30, 2015

• [PPC] Modify HTM and crypto intrinsics to inherit from GCCBuiltin

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Commits on Mar 25, 2015

• Add Hardware Transactional Memory (HTM) Support

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Commits on Mar 11, 2015

• Updated with list of possible improvements we are tracking internally

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Commits on Mar 10, 2015

• Change the generation of the vmuluwm instruction to be based on the MUL opcode.

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Commits on Mar 5, 2015

• While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) no…

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Commits on Mar 3, 2015

• Add the following 64-bit vector integer arithmetic instructions added in POWER8:

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Commits on Feb 20, 2015

• I incorrectly marked the VORC instruction as isCommutable when I added it.

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Commits on Feb 18, 2015

• This patch adds the VSX logical instructions introduced in the Power ISA 2.07. It also removes the added complexity that favors VMX versions of the three instructions.

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Commits on Feb 9, 2015

• This change implements the following three logical vector operations:

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