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qemu e1000 driver: use MII status reg for link up/down. From upstream…
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… via Brad.
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sthen committed Aug 28, 2011
1 parent 463f0a5 commit 87427bc
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Showing 3 changed files with 54 additions and 1 deletion.
3 changes: 2 additions & 1 deletion emulators/qemu/Makefile
Original file line number Diff line number Diff line change
@@ -1,11 +1,12 @@
# $OpenBSD: Makefile,v 1.74 2011/08/17 08:50:25 sthen Exp $
# $OpenBSD: Makefile,v 1.75 2011/08/28 11:21:05 sthen Exp $

# no success building on other archs yet
ONLY_FOR_ARCHS = amd64 arm i386 mips64 mips64el powerpc sparc sparc64

COMMENT = multi system emulator

DISTNAME = qemu-0.15.0
REVISION = 0
CATEGORIES = emulators
MASTER_SITES = http://wiki.qemu.org/download/ \
${MASTER_SITE_SAVANNAH:=qemu/}
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22 changes: 22 additions & 0 deletions emulators/qemu/patches/patch-hw_e1000_c
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@
$OpenBSD: patch-hw_e1000_c,v 1.1 2011/08/28 11:21:05 sthen Exp $

use MII status register for link up/down

--- hw/e1000.c.orig Fri Aug 26 02:20:32 2011
+++ hw/e1000.c Fri Aug 26 02:23:52 2011
@@ -624,10 +624,13 @@ e1000_set_link_status(VLANClientState *nc)
E1000State *s = DO_UPCAST(NICState, nc, nc)->opaque;
uint32_t old_status = s->mac_reg[STATUS];

- if (nc->link_down)
+ if (nc->link_down) {
s->mac_reg[STATUS] &= ~E1000_STATUS_LU;
- else
+ s->phy_reg[PHY_STATUS] &= ~MII_SR_LINK_STATUS;
+ } else {
s->mac_reg[STATUS] |= E1000_STATUS_LU;
+ s->phy_reg[PHY_STATUS] |= MII_SR_LINK_STATUS;
+ }

if (s->mac_reg[STATUS] != old_status)
set_ics(s, 0, E1000_ICR_LSC);
30 changes: 30 additions & 0 deletions emulators/qemu/patches/patch-hw_e1000_hw_h
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
$OpenBSD: patch-hw_e1000_hw_h,v 1.1 2011/08/28 11:21:05 sthen Exp $

use MII status register for link up/down

--- hw/e1000_hw.h.orig Fri Aug 26 02:21:00 2011
+++ hw/e1000_hw.h Fri Aug 26 02:21:40 2011
@@ -349,6 +349,23 @@
#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */

+/* PHY Status Register */
+#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
+#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
+#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
+#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
+#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
+#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
+#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
+#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
+#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
+#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
+#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
+#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
+#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
+#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
+#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
+
/* Interrupt Cause Read */
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */

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