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[globalisel][tablegen] Add support for extload.
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318068 91177308-0d34-0410-b5e6-96231b3b80d8
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dsandersllvm committed Nov 13, 2017
1 parent 372866c commit ed22c23
Showing 2 changed files with 36 additions and 14 deletions.
32 changes: 24 additions & 8 deletions test/CodeGen/AArch64/GlobalISel/select-load.mir
Original file line number Diff line number Diff line change
@@ -33,6 +33,7 @@

define void @sextload_s32_from_s16(i16 *%addr) { ret void }
define void @zextload_s32_from_s16(i16 *%addr) { ret void }
define void @aextload_s32_from_s16(i16 *%addr) { ret void }
...

---
@@ -95,8 +96,7 @@ body: |
; CHECK-LABEL: name: load_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK: %w0 = COPY [[COPY1]]
; CHECK: %w0 = COPY [[LDRHHui]]
%0(p0) = COPY %x0
%1(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
@@ -119,8 +119,7 @@ body: |
; CHECK-LABEL: name: load_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 0 :: (load 1 from %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
; CHECK: %w0 = COPY [[COPY1]]
; CHECK: %w0 = COPY [[LDRBBui]]
%0(p0) = COPY %x0
%1(s8) = G_LOAD %0 :: (load 1 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
@@ -221,8 +220,7 @@ body: |
; CHECK-LABEL: name: load_gep_64_s16_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[LDRHHui:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 32 :: (load 2 from %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRHHui]]
; CHECK: %w0 = COPY [[COPY1]]
; CHECK: %w0 = COPY [[LDRHHui]]
%0(p0) = COPY %x0
%1(s64) = G_CONSTANT i64 64
%2(p0) = G_GEP %0, %1
@@ -249,8 +247,7 @@ body: |
; CHECK-LABEL: name: load_gep_1_s8_gpr
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[COPY]], 1 :: (load 1 from %ir.addr)
; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[LDRBBui]]
; CHECK: %w0 = COPY [[COPY1]]
; CHECK: %w0 = COPY [[LDRBBui]]
%0(p0) = COPY %x0
%1(s64) = G_CONSTANT i64 1
%2(p0) = G_GEP %0, %1
@@ -508,3 +505,22 @@ body: |
%2:gpr(s32) = G_ZEXT %1
%w0 = COPY %2(s32)
...

---
name: aextload_s32_from_s16
legalized: true
regBankSelected: true

body: |
bb.0:
liveins: %w0
; CHECK-LABEL: name: aextload_s32_from_s16
; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
; CHECK: [[T0:%[0-9]+]]:gpr32 = LDRHHui [[COPY]], 0 :: (load 2 from %ir.addr)
; CHECK: %w0 = COPY [[T0]]
%0:gpr(p0) = COPY %x0
%1:gpr(s16) = G_LOAD %0 :: (load 2 from %ir.addr)
%2:gpr(s32) = G_ANYEXT %1
%w0 = COPY %2(s32)
...
18 changes: 12 additions & 6 deletions utils/TableGen/GlobalISelEmitter.cpp
Original file line number Diff line number Diff line change
@@ -3507,11 +3507,12 @@ TreePatternNode *GlobalISelEmitter::fixupPatternNode(TreePatternNode *N) {
// must be transformed into:
// (sext:[i32] (ld:[i16] [iPTR])<<unindexed>>)
//
// Likewise for zeroext-load.
// Likewise for zeroext-load and anyext-load.

std::vector<TreePredicateFn> Predicates;
bool IsSignExtLoad = false;
bool IsZeroExtLoad = false;
bool IsAnyExtLoad = false;
Record *MemVT = nullptr;
for (const auto &P : N->getPredicateFns()) {
if (P.isLoad() && P.isSignExtLoad()) {
@@ -3522,19 +3523,24 @@ TreePatternNode *GlobalISelEmitter::fixupPatternNode(TreePatternNode *N) {
IsZeroExtLoad = true;
continue;
}
if (P.isLoad() && P.isAnyExtLoad()) {
IsAnyExtLoad = true;
continue;
}
if (P.isLoad() && P.getMemoryVT()) {
MemVT = P.getMemoryVT();
continue;
}
Predicates.push_back(P);
}

if ((IsSignExtLoad || IsZeroExtLoad) && MemVT) {
assert(((IsSignExtLoad && !IsZeroExtLoad) ||
(!IsSignExtLoad && IsZeroExtLoad)) &&
"IsSignExtLoad and IsZeroExtLoad are mutually exclusive");
if ((IsSignExtLoad || IsZeroExtLoad || IsAnyExtLoad) && MemVT) {
assert((IsSignExtLoad + IsZeroExtLoad + IsAnyExtLoad) == 1 &&
"IsSignExtLoad, IsZeroExtLoad, IsAnyExtLoad are mutually exclusive");
TreePatternNode *Ext = new TreePatternNode(
RK.getDef(IsSignExtLoad ? "sext" : "zext"), {N}, 1);
RK.getDef(IsSignExtLoad ? "sext"
: IsZeroExtLoad ? "zext" : "anyext"),
{N}, 1);
Ext->setType(0, N->getType(0));
N->clearPredicateFns();
N->setPredicateFns(Predicates);

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