Some dummy cost model for s390x:

- Prefer short-imm instructions over ext-imm, when possible - Prefer Z10 instructions over Z9, when possible This hopefully should fix some dejagnu test fails on solaris git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79741 91177308-0d34-0410-b5e6-96231b3b80d8
babooppa6 · Aug 22, 2009 · 310ed13 · 310ed13
1 parent 3edd9bb
commit 310ed13
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Showing 2 changed files with 13 additions and 3 deletions.
diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td
@@ -94,19 +94,25 @@ class RREI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, RREForm, outs, ins, asmstr, pattern>;
 
 class RXI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, RXForm, outs, ins, asmstr, pattern>;
+  : I8<op, RXForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class RXYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, RXYForm, outs, ins, asmstr, pattern>;
 
 class RSI<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, RSForm, outs, ins, asmstr, pattern>;
+  : I8<op, RSForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class RSYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, RSYForm, outs, ins, asmstr, pattern>;
 
 class SII<bits<8> op, dag outs, dag ins, string asmstr, list<dag> pattern>
-  : I8<op, SIForm, outs, ins, asmstr, pattern>;
+  : I8<op, SIForm, outs, ins, asmstr, pattern> {
+  let AddedComplexity = 1;
+}
 
 class SIYI<bits<16> op, dag outs, dag ins, string asmstr, list<dag> pattern>
   : I16<op, SIYForm, outs, ins, asmstr, pattern>;

diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -324,6 +324,7 @@ def MOV8miy   : SIYI<0x52EB,
                      "mviy\t{$dst, $src}",
                      [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 
+let AddedComplexity = 2 in {
 def MOV16mi   : SILI<0xE544,
                      (outs), (ins riaddr12:$dst, s16imm:$src),
                      "mvhhi\t{$dst, $src}",
@@ -339,6 +340,7 @@ def MOV64mi16 : SILI<0xE548,
                      "mvghi\t{$dst, $src}",
                      [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
                      Requires<[IsZ10]>;
+}
 
 // sexts
 def MOVSX32rr8  : RREI<0xB926,
@@ -856,6 +858,7 @@ def MUL64ri16   : RII<0xA7D,
                       "mghi\t{$dst, $src2}",
                       [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 
+let AddedComplexity = 2 in {
 def MUL32ri     : RILI<0xC21,
                        (outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
                        "msfi\t{$dst, $src2}",
@@ -866,6 +869,7 @@ def MUL64ri32   : RILI<0xC20,
                        "msgfi\t{$dst, $src2}",
                        [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
                        Requires<[IsZ10]>;
+}
 
 def MUL32rm : RXI<0x71,
                   (outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),